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4,954 Views
Registered: ‎12-09-2008

Cannot generate test bench file

While attempting to generate a test bench file, no file is created. If i aim for a tbw file a console message saying 'Started : "Creating Tbw file".' would appear but no file would be created. If i opt for VHDL Test Bench file I get no messages at all, and, of course, the file is not created.

Note that this problem occurs only when I try to associate the test bench files with an entity containing references to other entities. Should I try the same procedure for simple entities, I have no problems whatsoever.

 

Thanks in advance.

 

Edit: I'm using Xilinx ISE 10.1.03 on Win XP SP2.

Message Edited by dusan.stamenkovic on 03-06-2009 01:17 PM
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1 Reply
Newbie klausraizer
Newbie
4,781 Views
Registered: ‎03-16-2009

Re: Cannot generate test bench file

I have the same problem over here.

 

 I try to add a test Bench to my .sch but i only get the message:

 

Started : "Creating Tbw file".

 

And nothing happens. 

 

Any solutions about that?

 

cheers  :)

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