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Newbie jordan23
Newbie
3,275 Views
Registered: ‎10-03-2011

Cascading Divider Generator 2.0

I'm very new to using Xilinx and FPGA work in general. I'm trying to use the divider generator in a cascaded manor. However, when I connect the input of a second divider generator to the output of the first, the result is not what I expect. For the quotient and remainder, I either get 0 and 0, or 255 and 0. Is there something else I need to do or set in the block? How can I cascade the divider block? Thanks.

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Xilinx Employee
Xilinx Employee
3,261 Views
Registered: ‎08-02-2011

Re: Cascading Divider Generator 2.0

Are you running your simulation long enough to account for the latency of both cores (which will depend on your configuration of the cores)?
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