cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
urodacus
Observer
Observer
1,048 Views
Registered: ‎04-28-2017

Change of custom IP in a block design

Hello,

I'm kinda new to BD and IP but I learned how to use it a bit for a design on Zynq.

If I'm here it's because I encountered a problem. I'm working on a project where the client change some aspects about what he wants so I have to adapt it.

I use a custom IP in a BD and when I upgrade it there is no problem except when the number of ports changes, Vivado ask me to upgrade it so I do but the synthesis won't go through, several error messages (one for each new port).

"Does not have matching formal port for component..."

I deleted the VHDL wrapper and asked Vivado to do it again and still the same. Is there a way to update it without any problem ?

Sorry for bad english and thanks :)

0 Kudos
8 Replies
dpaul24
Scholar
Scholar
1,042 Views
Registered: ‎08-07-2014

@urodacus,

I use a custom IP in a BD and when I upgrade it there is no problem except when the number of ports changes,

Yes, if there are unconnected ports of the IP, then Vivado will complain.

Did you try the validate block design feature after your changes to the custom IP?

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

0 Kudos
urodacus
Observer
Observer
1,037 Views
Registered: ‎04-28-2017

@dpaul24 I connected all the new ports and design is validated

0 Kudos
dpaul24
Scholar
Scholar
1,028 Views
Registered: ‎08-07-2014

@urodacus,

From you description I cannot guess any answers.

Is there a way to update it without any problem ?

As a workaround, take you custom IP completely out of the BD. Create a wrapper_BD without your custom IP. Then create a top level wrapper where you instiantiate the wrapper_BD, custom IP and connect both.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

0 Kudos
anusheel
Moderator
Moderator
1,001 Views
Registered: ‎07-21-2014

@urodacus 

Did you change custom IP? If yes, please check whether you are able to synthesize(standalone) it or not.
Also, while generating wrapper did you try using "Let Vivado Manage ..."?

Thanks
Anusheel

0 Kudos
urodacus
Observer
Observer
972 Views
Registered: ‎04-28-2017

@dpaul24i don't really know how to do that (excepted manually but that could take some time since if I remember correctly the signals from BD don't really have explicits names)

 

@anusheelYes I updated my IP :

changed the IP, synthetised it, re-saved it as if it was a new IP but I overwrited previous IP (i don't know if it's automatic so I did that).

I also let vivado manage and update the wrapper.

 

I had the same issue with the last time I tried updating an IP and I had to create a new project and instantiate it again in a new project since deleting it and instantiating again in the same project didn't work.

Sorry for the time I took to reply and thanks.

0 Kudos
anusheel
Moderator
Moderator
962 Views
Registered: ‎07-21-2014

@urodacus 

Are there any warnings or errors reported at the time of upgrading the IP? If not, can you please share a small test with us. 

Thanks
Anusheel 

0 Kudos
dpaul24
Scholar
Scholar
953 Views
Registered: ‎08-07-2014

@urodacus,

@dpaul24i don't really know how to do that (excepted manually but that could take some time since if I remember correctly the signals from BD don't really have explicits names)

As it is an alternative solution, it has its merits and demerits. Which solution you choose is your decision.

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

0 Kudos
urodacus
Observer
Observer
950 Views
Registered: ‎04-28-2017

@anusheelI think I found the solution. the .vhd in my project (with the BD) are not updating correctly. If I create a new component in my IP porject, it shows but the one already existing won't update so i copy/pasted the new ones (with new ports), it seems to work.

Now I got a problem with SDK, the peripheral drivers aren't updating in my project but that's another issue i guess.

0 Kudos