cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
bill.whitehead
Contributor
Contributor
2,484 Views
Registered: ‎09-02-2013

Clock Wizard 6.0 not supported in module reference (xilinx.com:ip:clk_wiz:6.0)

Jump to solution

I am working to port an older design from ISE 14.7 to Vivado 2018.2.  I had used the older Clock Wizard 3.6 in ISE 14.7 for an MMCM core.  I have been successful as all of the other cores, except for the Clock Wizard.  I was able to set up the new 6.0 version to be exactly how I had the previous version.  It provide instantiation templates in verilog as well.  I use a block diagram for the top level with some new custom IP I created and other IP from the IP Catalog.  The bulk of my previous design is brought in as a module reference.  Down a couple layers in hierarchy is the MMCM.  I used the new instantiation template and put that into my code. I have created a TCL script to produce my Block Diagram. 

 

After the block diagram is complete, I run the following and get this error:

 

update_module_reference aeye_vivado_top_st_top_0_0
ERROR: [filemgmt 56-181] Reference 'st_top' contains sub-design file 'c:/Projects/SmartTracker/aeye_vivado/aeye_vivado.srcs/sources_1/ip/HISPI_MMCM/HISPI_MMCM.xci'. This sub-design is not allowed in the reference due to following reason(s):
The 'xilinx.com:ip:clk_wiz:6.0' core does not support module reference.
ERROR: [Common 17-39] 'update_module_reference' failed due to earlier errors.

Due to this error, then I can't have a Clk_Wiz component used in a module reference?  What is recommended by Xilinx?  What do others due when trying to use an MMCM in their designs?

 

I thought I would at least try synthesis just to see.  I get the following:

 

ERROR: [filemgmt 56-181] Reference 'st_top' contains sub-design file 'c:/Projects/SmartTracker/aeye_vivado/aeye_vivado.srcs/sources_1/ip/HISPI_MMCM/HISPI_MMCM.xci'. This sub-design is not allowed in the reference due to following reason(s):
The 'xilinx.com:ip:clk_wiz:6.0' core does not support module reference.

If I am stuck with this, then what is the recommended method for using a Clk Wiz component in Vivado?  I tried to search and find anyone else who has had this problem.  No luck.  That is why I posted here.  Thanks for any insights or help.

 

Bill

 

 

 

 

0 Kudos
Reply
1 Solution

Accepted Solutions
shameera
Moderator
Moderator
2,464 Views
Registered: ‎05-31-2017
0 Kudos
Reply
1 Reply
shameera
Moderator
Moderator
2,465 Views
Registered: ‎05-31-2017
0 Kudos
Reply