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Registered: ‎11-29-2019

Clock issue in packaging IP

Hi everyone. I need help, please. I have an IP with AXIStream input and output. I try to package IP and when I want configure my signal clock with command 'Auto Infer Single Bit Interface' Vivado crashes and closes himself. This happens only with clock signal. If I assign reset or other I haven't problems. I tried with different versions of Vivado in Windows and Ubuntu. Now I need to use 2018.1 Version. Someone has a solution for this issue? thank you very much

FT
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: Clock issue in packaging IP

Hi, 

Is it possible to upload rtl or bd  that your are packaging?

Other way is, instead of the command, can you try if inserting attributes in RTL helps?

ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of clk_in: SIGNAL is "xilinx.com:signal:clock:1.0 clk_in CLK";

(* X_INTERFACE_INFO = "<interface vlnv> <interface_name> <logical_port_name>" *)

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