Clocking Wizard 6.0 not locking

[ewalls]

I am currently using Vivado 18.3 and have placed a Clocking Wizard 6.0 IP block into my design.

Sadly the lock output is never asserting.  It is a straightforward block so I'm a bit uncertain as to why this should be.

I'm inputting a 100MHz system clock and generating a single 19.2 MHz output Clock with Lock.

I'm using a Zedboard and I've connected the Lock signal to one of the onboard LEDs.  I've also connected a NOT Lock to another LED so that at least one is always lit (just so I can reassure myself I've actually connected things to pins).

See attached screenshots of the design and configuration of the clocking wizard.

Why isn't the Lock output asserting (high)?

[drjohnsmith]

So how does the simulation look ?

You have two choices here,

   You find these sort of errors by traceing back the fault in simulation,

or

     you randomly guess what the problem is , fix it and check again on the board.

it could be because of reset,

it could be because the clock wisard has not be configured right by the processing system

  it could be the processing system is not working,

it could be ?????

Once simulation works , then you hit the board.

[ewalls]

Good point and well made.  I hadn't thought to simulate it as it seemed so simple however as you can see in the attached screenshot when simulated it does actually provide a clock and asserts a lock signal so I'm still confused why this isn't happening in HW.

The lock is active HIGH isn't it?  That is what the datasheet seems to imply.

Still very confused.

[drjohnsmith]

In your design, your using the dynamic reconfiguratoi port of the clock wizard,

    bu tthats not present in the sim, so I suspect they are not the same thing,

Its a guess, but try removing the dynamic config port from your IP, and see if thats whats causing the problem.

[ewalls]

---

@drjohnsmith wrote:

In your design, your using the dynamic reconfiguratoi port of the clock wizard,

    bu tthats not present in the sim, so I suspect they are not the same thing,

Its a guess, but try removing the dynamic config port from your IP, and see if thats whats causing the problem.

---

The dynamic config was put in to give me access to the register set so that I could have the linux kernel read if the clock was locked or not before proceeding to configure an external device.

Anyhow, that has now been removed so the clock wizard is literally just a 100MHz input, a 19.2MHz output.  An active low reset and a Locked ouput.

I have simulated this and it seems to work fine but when it is put in hardware, nothing.  No clock, no lock....

I've driven both signals out to a PMOD pin (on the Zedboard) and attached a 'scope.  There is nothing on either output.  No clock and no lock.

I'm utterly stumped!

[drjohnsmith]

have you checked the reset is low ?

is the device configured ( done led on ? )

[ewalls]

---

@drjohnsmith wrote:

have you checked the reset is low ?

is the device configured ( done led on ? )

---

The device is configured (led is on).  I haven't physically checked the reset.  I'll check.

[drjohnsmith]

IM afraid your down to good old fashion debugging

   its goign to be soimething simple..

[ewalls]

OK. 

I'm more "Old School" FPGA and only recently been introduced to the Zynq.

The reset is working in simulation but when brought out to an external pin it looks like the PL is staying in reset.  Does the Zynq SoC need the PS to be programmed before the PS system clock and reset do their thing? (Can't believe I'm asking this question really...)

[drjohnsmith]

Thats a good question

The systems I use , the PS is always programmed first to then bring up the PL, even if its a noddy boot,

BUT

I have memory that the PL can be bought up on own, but that might be via JTAG only.

sorry , not more helpful,