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Contributor
Contributor
3,909 Views
Registered: ‎10-27-2010

Clocking Wizard Output Jitter

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Hello,

 

I was interested in directly instantiating a PLLE2_ADV primitive in my code, but wanted to take advantage of the "minimize output jitter" option within the clocking wizard for a PLL. Does anyone know if there's a generic value I can set to force the PLLE2_ADV to do this? Or is this something that is applied outside the PLLE2_ADV element? 

 

I created two OOC IPs, one with "Balanced" selected , and the other with "Minimize Output Jitter" selected, and all other settings the same. I noticed the clocking wizard created different generics values for BANDWIDTH, CLKFBOUT_MULT and CLK0_DIVIDE.  I also noticed that the verilog wrapper file has this line that shows use_min_o_jitter=true or false according to my jitter setting within the wizard.

 

(* CORE_GENERATION_INFO = "clk_wiz_output_jitter,clk_wiz_v5_3_1,{component_name=clk_wiz_output_jitter,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)

 

This is targeted on a Virtex7 device. 

 

Thanks.

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Historian
Historian
7,125 Views
Registered: ‎01-23-2009

Re: Clocking Wizard Output Jitter

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would there be any difference between a direct instantiation of a PLLE2_ADV primitive using the exact same generics values provided by the clocking wizard tool

 

No, they would be exactly the same. The clocking wizard is instantiating the PLLE2_ADV primitive; within the IP (or CoreGen, I am not sure if you are using Vivado or ISE) directory structure you can find the actual module created, which has the direct instantiation of the primitive.

 

Avrum

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Scholar austin
Scholar
3,892 Views
Registered: ‎02-27-2008

Re: Clocking Wizard Output Jitter

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n,

 

This selects either a higher, or lower bandwidth for the phase detector filter pole.  I believe the wide setting is > 300 KHz, and the low setting is < 100 KHz (roughly).  Not all that much difference (at most 3:1).  So depending on the source clock jitter, you will get less output jitter with the low or narrow bandwidth setting) minimize output jitter).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
Historian
3,888 Views
Registered: ‎01-23-2009

Re: Clocking Wizard Output Jitter

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The CORE_GENERATION_INFO (as the name implies) is the information that the core generator used to generate the core. Generally, there is a one to one correspondence between this information and the boxes your filled in or the options you selected in the graphical user interface of the core. So the "use_min_o_jitter" is the input to the process. From the RTL point of view, this is in the format of an attribute, but it is not one that affects the RTL (it is only used by the core generator itself). Once the core is generated it doesn't do anything (and is basically similar to a comment).

 

As you have discovered, the tools have two different mechanisms for managing the jitter transfer. One is by controlling the loop feedback bandwidth (BANDWIDTH). When the PLL detects a phase error between the input and feedback clock, this generates an error response. This error response then affects the voltage of the voltage controlled oscillator. The BANDWIDTH determines how it affects it - and there is a tradeoff. Set one way, the PLL adjusts quickly to this phase error, but as a consequence it allows jitter from the input through to the output. Set the other way, it filters out the jitter, but makes the PLL slower to respond to phase changes of the input clock (increasing phase error). Depending on what you are doing with this clock, one behavior may be preferable over the other, but it is implementation dependent...

 

The other mechanism is in determining the VCO frequency. The PLL has one multiplier and two dividers. There are often several solutions for the values of these multipliers and dividers for getting a particular output frequency from a particular input. For example, just the simple case of generating a 200MHz output from a 200MHz input can be done with

  - multiply by 5, divide by 5

  - multiply by 4, divide by 4

  - multiply by 4.25, divide by 4.25 (some of the multipliers and dividers can be in increments of 0.125)

 

These too will give different characteristics in terms of jitter attenuation, responsiveness, phase error, power consumption, ...

 

So, in the end, this is one of the most valuable aspects of the core generator/IP catalog - it can make decisions appropriate to what you want, and ultimately give you information on the resulting jitter of the implemented solution.

 

Avrum

Contributor
Contributor
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Registered: ‎10-27-2010

Re: Clocking Wizard Output Jitter

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Thank you both for the very informative answer.  Seems like using the clocking wizard is advantageous in scenarios where your input/output clocks may change in the design and allows for optimal settings in terms of jitter.

 

 

Based on your response, would there be any difference between a direct instantiation of a PLLE2_ADV primitive using the exact same generics values provided by the clocking wizard tool (from an implementation onto the part standpoint)? 

 

 

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Historian
Historian
7,126 Views
Registered: ‎01-23-2009

Re: Clocking Wizard Output Jitter

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would there be any difference between a direct instantiation of a PLLE2_ADV primitive using the exact same generics values provided by the clocking wizard tool

 

No, they would be exactly the same. The clocking wizard is instantiating the PLLE2_ADV primitive; within the IP (or CoreGen, I am not sure if you are using Vivado or ISE) directory structure you can find the actual module created, which has the direct instantiation of the primitive.

 

Avrum

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