03-15-2018 03:02 AM
I have designed a custom multiplex logic in RTL and created a IP out of it. When I tried adding that IP to block design and validate it throws the following error.
[BD 41-967] AXI Interface Pin /FER_0/ONE_F1_m1_axi_rx is not associated to any clock pin. it may not work correctly.
More details are given in the Screen shot attached. PFA
03-15-2018 03:30 AM
From the error message it looks like m1_axi_rx interface of your custom IP doesn't have a clock interface defined. Please note that it is mandatory to associate/define a clock & reset for any AXI interface.
Edit m1_axi_rx interface in IP packager and define the associated clocks to over come the warning.
03-15-2018 03:33 AM
AXI interface is required at least one clock port.
So, vivado said "[BD 41-967] AXI Interface Pin /FER_0/ONE_F1_m1_axi_rx is not associated to any clock pin. it may not work correctly."
Would you refer AXI interface specification, if you want to know detail ?
03-19-2018 02:34 AM
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