Combination Logic Validation failed in Block design

[naveen_s]

Hi All,

        I have designed a custom multiplex logic in RTL and created a IP out of it. When I tried adding that IP to block design and validate it throws the following error. 

 [BD 41-967] AXI Interface Pin /FER_0/ONE_F1_m1_axi_rx is not associated to any clock pin. it may not work correctly.

 More details are given in the Screen shot attached. PFA

Regards

Naveen S

[syedz]

@naveen_s,

From the error message it looks like m1_axi_rx interface of your custom IP doesn't have a clock interface defined. Please note that it is mandatory to associate/define a clock & reset for any AXI interface.

Edit m1_axi_rx interface in IP packager and define the associated clocks to over come the warning. 

--Syed

[watari]

Hi @naveen_s

AXI interface is required at least one clock port.

So, vivado said "[BD 41-967] AXI Interface Pin /FER_0/ONE_F1_m1_axi_rx is not associated to any clock pin. it may not work correctly."

Would you refer AXI interface specification, if you want to know detail ?

Best regards,

[anatoli]

Hello @naveen_s,

This topic is still open and is waiting for you.

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 

If this is not solved/answered, please reply in the thread.

Thanks in advance and have a great day.