11-23-2015 10:59 AM
BLUF: Is there an alternative IP core to the Comparator v8.0 core that is compatible with Virtex-5, -6 and -7 FPGAs?
I was looking for an IP core to perform a greater-than-or-equal-to operation on 2 unsigned integers and found the Comparator v8.0 core; however, not only is it discontinued, it is not supported for the FPGAs I am interested in, i.e. Virtex-5, -6, and -7. I have scoured these forums and Google trying to find an alternative to this IP Core for the above-mentioned devices, but the only alternatives I have found are:
The DSP block option just seemed a bit awkward since you have to instantiate the DSP primitive directly (without the benefit of an IP Macro) and the HDL option is less than desirable because I would like to have a little more control over the pipelining/latency of the implementation. If these are my only two options, then I'm okay with that, but I wanted to make sure I wasn't overlooking some new IP core that replaced the old one.
11-23-2015 11:10 AM - edited 11-23-2015 11:22 AM
The Comparator v8.0 Core can be used on a Virtex-5 device by generating the core for a Virtex-4 device and implementing that netlist on a Virtex-5 device.
You have an option of DSP Macro as well:
Few more alternatives to the Comparator can be found here:
11-23-2015 11:32 AM
Thank you for the quick reply!
Yes, I have tried the DSP48 Macro, although I only have access to DSP48 Macro v2.1 (using ISE 13.2) which doesn't have a simple way to set up a comparator (or perhaps I don't know what instruction to use). The above-mentioned link, Implement it with a DSP48 block, says the macro doesn't support the pattern detector operation necessary for a comparator, which is why you have to instantiate the DSP primitive directly.
I did not know that the Comparator v8.0 implementation for V-4 was also compatible for the V-5, but I am looking for a solution that is simultaneously compatible with V-5, -6 and -7.
11-23-2015 11:48 AM