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Observer
Observer
11,224 Views
Registered: ‎09-01-2014

Conditional code in component.xml ?

I have a need to, based on combination of parameters that user has selected for the IP in his BD, decide which .xdc file(s) to include in the IP build process, such as:

 

        if (based-on-user-selected-IP-GUI-option) then

            include file1.xdc

        else

            include file2.xdc

        endif

 

Any ARs, AppNotes or examples on how to go about that?

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Moderator
Moderator
11,222 Views
Registered: ‎06-24-2015

Hi @chili.chips,

 

I think this AR should help you:
http://www.xilinx.com/support/answers/57546.html

Thanks,
Nupur
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Moderator
Moderator
11,207 Views
Registered: ‎06-24-2015

Hi @chili.chips,

 

Is your query resolved? If you need any further help, please let us know.

Thanks,
Nupur
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Observer
Observer
11,202 Views
Registered: ‎09-01-2014

That AR is very interesting, but it unfortunatelly does not address what I'm trying to do, which is:

 

   1) keep the IP reconfigurable in user BD

   2) but have it pick up proper subset of .XDC and .V files for the combination of options that user has selected through the IPI GUI

 

Note that the user may put down multiple instances of this IP on his BD canvas, and have different parameter selection for each, hence the IP would need to get built with different set of .XDC and .V files for each instance. And, given the rather large number of parameter combinations, I really need to support that with only one component.xml file.

 

  By googling around, I ran into the following link:

         https://sourceforge.net/p/elphel/EclipseVDT/ci/55f38d4cc01a8497aae5171092598046cc2b60a4/tree/vdt/tools/Xilinx_Vivado/vivado_opt_place.xml

  

  which comes with the kind of construct I'm looking for:

<if SkipPowerOptimization="false">
<!-- Run power optimization -->
"power_opt_design"
"%quiet_pwr_opt"
"%verbose_pwr_opt"
"\n"
</if>
 
Another idea is to bundle .xit file into my component.xml, then have that TCL do some post-processing work.
 
But, the problem is that I don't have much time to spend experimenting, which is where a proven example or step-by-step guideline would go long ways to help be quickly get there.
 

 

 

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Scholar
Scholar
11,183 Views
Registered: ‎06-05-2013

@chili.chips As far as i know there arent any examples like this. We wont recommend customers to modify/update xml files which are in install area. I havent tried this myself but i think unmanaged constraint may help you here, check this thread

https://forums.xilinx.com/t5/Vivado-TCL-Community/Using-IF-in-XDC-Files/td-p/560897

-Pratham

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Observer
Observer
11,130 Views
Registered: ‎09-01-2014

unmanaged constraints are indeed helpful to know about and I believe they could be drawn upon to crack this problem open.

 

Ultimately however, what I'm looking for is ability to define *Enablement Dependency* in the File Groups section of IP-XACT GUI in the similar way as that can already be done for Ports and Interfaces

component.PNG

  • Any chance for extending Enablement Dependency feature to files in one of the upcoming Vivado releases?

 

Also, is there a way to propagate configuration parameters from the IPI GUI into this "unmanaged constraints TCL"?

I know they get propagated from GUI to Verilog parameters / VHDL generics, but am not sure how to pick them within TCL to so make the constraints sensitive to the combinaton of IP settings that the user has entered within IPI GUI.

 

Alternatively, is there a way to embed contraints' TCL in RTL, in which case I could use Verilog conditionals to pass the GUI settings into constraints, such as:

       if (GUI-ENTERED-PARAMETER-VALUE == XYZ) then

            /*synthesis_tcl_begin

               apply-such-and-such constraint

            synthesis_tcl_end */

         

I believe that Synopsys DC can take constraints which are embedded in RTL...

 

 

 

 

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Observer
Observer
10,956 Views
Registered: ‎09-01-2014

here is an interesting lead on How-to-Propagate-Parameters-from-Verilog-to-TCL, but unfortunatelly does not solve the problem:

 

https://forums.xilinx.com/t5/Synthesis/Read-value-of-hdl-verilog-parameters/td-p/419719

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