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_nicolas_
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Registered: ‎09-27-2019

Connections on Vivado block design

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I created the block block design in the image below, according the the orange line, the some_bus inouts of the two entities (dummy_0 and dummy_1) are connected.

block_design.png
After generating the output products (with the global synthesis option), the generated structure for the block design looks like:

--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
--Date        : Sat Jan  9 21:45:04 2021
--Host        : nicolas-desktop running 64-bit Arch Linux
--Command     : generate_target design_1.bd
--Design      : design_1
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
  port (
    some_output_0 : out STD_LOGIC
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;

architecture STRUCTURE of design_1 is
  component design_1_dummy_1_0_0 is
  port (
    some_bus : inout STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  end component design_1_dummy_1_0_0;
  component design_1_dummy_0_0_0 is
  port (
    some_bus : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    some_output : out STD_LOGIC
  );
  end component design_1_dummy_0_0_0;
  signal dummy_0_0_some_output : STD_LOGIC;
  signal NLW_dummy_0_0_some_bus_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_dummy_1_0_some_bus_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
  some_output_0 <= dummy_0_0_some_output;
dummy_0_0: component design_1_dummy_0_0_0
     port map (
      some_bus(1 downto 0) => NLW_dummy_0_0_some_bus_UNCONNECTED(1 downto 0),
      some_output => dummy_0_0_some_output
    );
dummy_1_0: component design_1_dummy_1_0_0
     port map (
      some_bus(1 downto 0) => NLW_dummy_1_0_some_bus_UNCONNECTED(1 downto 0)
    );
end STRUCTURE;

 

So they are not connected. How can I let Vivado make the connection?

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joancab
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Registered: ‎05-11-2015

inouts are only for connection to physical pins, not for internal connections.

An inout port appears (at the block edge) as three pins: one input, one output and a direction pin. These are connected to the corresponding buffer and you have a single-pin with bidirectional capabilities. But inside of the FPGA there are no bidirectional wires.

You cannot use the inout scheme between FPGA blocks. It's dangerous. Each connection end will have a driver (putting 1's or 0's) and a receiver. You need to make sure that both drivers are not enabled at the same time. That's a problem. Even if you enable/disable them with the same signal, the propagation path to them may be different and have glitches that will blow up something after some time.

If you need a bidirectional communication between A and B, just have each block with an input and an output and connect in-to-out. Zero risk, full duplex comm, why complicating your life?

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joancab
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Registered: ‎05-11-2015

inouts are only for connection to physical pins, not for internal connections.

An inout port appears (at the block edge) as three pins: one input, one output and a direction pin. These are connected to the corresponding buffer and you have a single-pin with bidirectional capabilities. But inside of the FPGA there are no bidirectional wires.

You cannot use the inout scheme between FPGA blocks. It's dangerous. Each connection end will have a driver (putting 1's or 0's) and a receiver. You need to make sure that both drivers are not enabled at the same time. That's a problem. Even if you enable/disable them with the same signal, the propagation path to them may be different and have glitches that will blow up something after some time.

If you need a bidirectional communication between A and B, just have each block with an input and an output and connect in-to-out. Zero risk, full duplex comm, why complicating your life?

View solution in original post

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_nicolas_
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inouts are only for connection to physical pins, not for internal connections.
    Got it, not and option for connecting components to each other when using the block design.

The goal would be to instantiate many components (lets say around 15) on the block design, and connecting them all to each others (point to multi-point connections and multi-point to point connections, otherwise I would use a custom interface) in a clean way, meaning not too many wires. Each component has a lot of connections, lets say around 100.
When instantiating all the components and connecting them in my own top HDL file, the bitstream can be generated and everything works just fine.

For the reason that the design should be editable by engineers with very little or no HDL knowledge, it would be very handy to be able to use the block design for instantiating and connecting components (in a graphical way).

If you need a bidirectional communication between A and B, just have each block with an input and an output and connect in-to-out. Zero risk, full duplex comm, why complicating your life?
    - To reduce the amount of wires
    - In my own top file I would instantiate multiple components with an output port, these output ports are then port mapped to a vector (wire/signal) and that vector would then be used as input for another component. In the block design I can do this using the concat IP, but I would require 6 instances of the concat IP and again a mess of wires.
Therefore I decided to add the complete vector as inout to every component and drive unused outputs to 'Z' (a generic is used to decide the output that is to be driven to '1' or '0') and the synthesis does the rest. However as it is impossible to connect multiple outputs together on the block design, this is no longer an option and I am forced to use the concat IP? (Also this is what I mean by multi-point to point)

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joancab
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Nobody cares about "the amount of wires". And you shouldn't. These are connections in silicon, that is there, whether used or not. I may understand as a reason if the design gets congested and doesn't route. But bidirectional connections inside an FPGA has more problems than advantages. And you will need some protocol to decide when blocks talk and listen, deal with clashes in a quick and safe manner, etc. If you really need to reduce connections I would first think about serializing comms at a higher speed. I doubt that Vivado lets you connect two drivers to the same net without raising hell. I know, "there aren't two drivers because only one will be active", but potentially there could be and that is what Vivado checks for. I don't think it will understand, for example, that the enables are driven by a complementary signal.

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joancab
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Another thing: 'Z' doesn't exist inside of the FPGA. Only in the rosy simulation World and outside of output pins after the driver being disabled.

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joancab
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I don't know what you want to achieve but I was once working on some kind-of neural networks with such a multi-block scheme and the way I had the communications between blocks was kind of a mesh network so blocks only need to connect to another one and messages are routed through the blocks and processed only at the destination one. Kind of the internet, you don't have your computer connected to every other computer in the World (directly)

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_nicolas_
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The protocol and communication are both working correctly, but as implemented now, for each module about 7 wires have to be connected manually resulting in around a little less then 150 manual connections... Connecting everything in HDL is faster (and clearer, as you can use types/records and such, to me) than using the block design, but it will be an inconvenience for engineers without the HDL knowledge (has to be used and edited in the coming years by others).

Anyways, thank you joancab for the quick and clear feedback!

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joancab
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Cannot you create multi'signal ports, kind of AXI? I know that Vivado recognizes AXI signals and bundles them together in handy packets. Maybe there is a trick to pack your specific set of signals (?)

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_nicolas_
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When using interfaces (such as AXI) only point to point connections are possible.
More specifically, connecting a master interface to two or more slave interfaces is not allowed / possible.
That is why that is not really an option for the current implementation.

At the moment I "flattened" my signals to a single std_logic_vector, with an interface you can add multiple "fields" to a single wire.

I am just using a very basic parallel bus with control signals between the instantiation of the components, so no support for "routing" really, a serial bus or adding routing is indeed an option as well.

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