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Participant
Participant
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Registered: ‎06-17-2015

Constant IP Problem during timing simulation

I have declared a 31 bit constant using the constant IP block:

 

ConstIP.PNG

When I do a timing simulation the constant bits show up as Z's going into the In0 input of the concatenation block:

Concat.PNG  

The Synthesis schematic shows the correct implementation of the constant IP block: 

schematic.PNG

Can somebody explain to me why the constant values are being displayed as Z's on the timing simulation and what should I do to correct this issue?

Thanks for all your help.

 

Jorge Gonzalez

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Scholar
Scholar
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Registered: ‎06-20-2017

Looks like a bug.  To dig deeper, right click on the schematic and go to source.

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