07-13-2016 06:43 AM
I'm having difficulty constraining (in .xdc) my pins for communication interfaces in general (SPI and IIC at least). For example, in my Block Design, I created an Interface Port of type spi_rtl. I connected that interface port to the AXI Quad SPI IP in my Block Design. Now, my interface is composed of the following signals:
What puzzles me is the _i, _o and _t for each IO. I'm don't know how to write, in my .xdc, that this io0 will be used as MOSI. Will this be the correct way to go (and I ignore the _i and _t pins?):
set_property PACKAGE_PIN C16 [get_ports adc_spi_io0_o]
set_property IOSTANDARD LVCMOS18 [get_ports adc_spi_io0_o]
07-13-2016 07:24 PM
If the design has a communication interface via Quad SPI, you describe the constraint for input and output.
I guess "adc_spi_io*_i" is for input and "adc_spi_io*_o" is for output and "adc_spi_io*_t" is for control of output buffer.
I describe the example for it.
Please modify it by yourself.
set_input_delay -max <maximum value> -clock <related clock> <port name>
set_input_delay -min <minimum value> -clock <related clock> <port name>
set_case_analisys <1 or 0 (Enable output mode)> <control pin of output buffer>
set_output_delay -max <maximum value> -clock <related clock> <port name>
set_output_delay -min <minimum value> -clock <related clock> <port name>
I guess you need to add "-clock_fall" option. But it's related with your design.
07-21-2016 05:52 AM
thanks for your answer. This, combined with the following link I found, I think I have all the elements to needed!