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Participant aoliveri2
Participant
5,061 Views
Registered: ‎07-21-2016

[Constraints 18-376] set_input_delay: more than one reference clocks specified warning In Ethernet Subsystem core 7.0.

This critical warning is seen after porting Ethernet Subsystem from version 6.2 to version 7.0.  These 2 constraints in the *eth_mac_0_clocks.xdc file are what the error is being thrown on.  The constraints did exist in version 6.2.  Why does the critical warning occur with the 7.0 version?  The change from 6.2 to 7.0 was done in order to fully port a design from Vivado version 14.4 to version 16.2

 

# The following constraints work in conjunction with IDELAY_VALUE settings to
# check that the GMII receive bus remains in alignment with the rising edge of
# GMII_RX_CLK.

set_input_delay -clock $rx_clk -max 5.2            [get_ports {gmii_rxd[*] gmii_rx_er gmii_rx_dv}]
set_input_delay -clock $rx_clk -min 0.5 -add_delay [get_ports {gmii_rxd[*] gmii_rx_er gmii_rx_dv}]

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Scholar drjohnsmith
Scholar
4,964 Views
Registered: ‎07-09-2009

Re: [Constraints 18-376] set_input_delay: more than one reference clocks specified warning In Ethernet Subsystem core 7.0.

I don't know

 

BUT

 

when similar questions have been asked about critical warnings in xilinx IP blocks, the answer is on the lines of," if it does not stop you generating a bit file, then its not a problem !!"

 

 

can you try re generating the core a new to a new name ?

 

I have seen all sorts of problems trying to update IP cores in Vivado, and thats between say 16.1 to 16.2,

    going from 14.4 to 16.2 is a BIG step that I'm 99.9 % certain no one has tested..

 

 

 

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