Core Generator Producing Too Many Block Memories

[nathan_clarke]

I'm using ISE 12.3 core generator to generate (for Virtex 6) a simple dual-port memory with port A (write port) 128b wide by 256 deep, and port B (read port) 32b wide by 1024 deep (i.e. a 1:4 port aspect ratio).  I understand that the maximum BRAM bus width is 72b, so coregen needs to use at least two 36K BRAMs to implement a 128b wide bus, but for some reason it is using up 4 BRAMs.  Can anyone explain why it needs 4 BRAMs rather than 2?

This seems to be determined by the port aspect ratio.  If I change port B to be 128b wide by 256 (i.e. a 1:1 port aspect ratio), then coregen requires only 2 BRAMs.

Cheers,

Nathan

[gszakacs]

Are you sure that Coregen is using 4 36Kb RAMs?  I would have thought that this configuration would

fit in 4 18Kb RAMs, which in effect only uses two 36K RAM blocks.

-- Gabor

[nathan_clarke]

Yes, coregen's summary information reports that 4 36K BRAMs will be used.  Also after I instantiate and implement the design, PlanAhead shows 4 36K BRAMs.  Any idea why so many?

[nathan_clarke]

OK, this is really bugging me.  I have run into similar problems generating a 512x64 true dual-port memory.  In this case the block memory generator (v. 4.3), in the information field on page 5, reports that it needs 2 36K BRAMs, rather than just one.

Experimenting further, I tried 512x36, and it reports needing 1 36K BRAM, rather than 1 18K BRAM.

Is this a bug?  I guess I can just instantiate the primitives directly, but I figured it ought to be easier, more managable and more efficient (esp. for complex memories) to use coregen.  Clearly, it's not very efficient :{

Cheers,

Nathan

[nathan_clarke]

BTW, I'm targetting V6LX240T.  I've read the UG363 and I don't see any issues with the aspect ratios I require.

 ... Correction:  Table 1-5 of UG363 explains it.  In true dual-port mode, the 36K BRAM supports only up to 36 bit widths, and the 18K BRAM only goes up to 18 bits wide.