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Visitor caycay
Visitor
7,070 Views
Registered: ‎06-16-2013

Core Generator: Square Root I/O Sizes

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Hi all!

 

I am trying to include one square root block generated by the Core Generator. I am using v14.1.

 

I have a couple of issues: When I generate the block for 31b input - 16b output , the generated Verilog file is 32b input and 16b output. When I generated it for the 32b input - 17b output, the generated Verilog file is 32b input and 24b output. I couldn't understand why CoreGen says different bitwidth than the generated Verilog file bitwidth. Can anyone suggest me what points I am missing?

 

Thanks!

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Xilinx Employee
Xilinx Employee
10,895 Views
Registered: ‎08-02-2011

Re: Core Generator: Square Root I/O Sizes

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Yes, AXI Stream protocol requires data ports to terminate on byte boundaries. Thus ports are sign extended. This should be explained in the PG.
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Xilinx Employee
Xilinx Employee
10,896 Views
Registered: ‎08-02-2011

Re: Core Generator: Square Root I/O Sizes

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Yes, AXI Stream protocol requires data ports to terminate on byte boundaries. Thus ports are sign extended. This should be explained in the PG.
www.xilinx.com
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Visitor caycay
Visitor
7,047 Views
Registered: ‎06-16-2013

Re: Core Generator: Square Root I/O Sizes

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Thank you very much for your reply.

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