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Explorer
Explorer
5,048 Views
Registered: ‎07-13-2010

CoreGEN IP RAM output 0

Hi,

my problem is that when I stop reading from RAMs, which were generated with CoreGEN, the output of RAM is still the last value I've read. Is there a way using CoreGenerator to make RAMs give 0 in it's output when read_enable is "false" ?

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4 Replies
Xilinx Employee
Xilinx Employee
5,034 Views
Registered: ‎01-03-2008

Re: CoreGEN IP RAM output 0

Some FPGA families (like Virtex-5) have a BlockRAM have a SSRA/SSRB pins that provide a synchronous set or reset to the output port.   This may not be an option in the CoreGen memory core, so you would need to modify the HDL code to add it to your design.

 

Setting the outputs to zeros, because the RAM was not enabled and read is unusual as the data for any address could be zero.

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Instructor
Instructor
5,023 Views
Registered: ‎07-21-2009

Re: CoreGEN IP RAM output 0

Following up on Ed McGettigan's post...

 

For Virtex-5, see UG190 v5.3 page 125:  Block RAM Port Signals.  See Set/Reset - SSR[A|B] description.  Also note the description of the SRVAL attribute.

 

For Virtex-6, see UG363 v1.5 page 23-24:  Block RAM Port Signals.  See Set/Reset description.  Also note the description of the SRVAL attribute.

 

For Spartan-6, see UG383 v1.3 page 20-21:  Block RAM Port Signals.  See Set/Reset description.  Also note the description of the SRVAL attribute.

 

- Bob Elkind

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Explorer
Explorer
4,962 Views
Registered: ‎07-13-2010

Re: CoreGEN IP RAM output 0

I'm using Virtex-4. In CoreGen there is an option to use SSR[A|B]. Unfortunately, when I tried to simulate RAMs using "Block Memory Generator" with SSR[B] pin, the output of RAMs is still the last value read. It seems that SSR pin is somethow not even responding to signals.... (during simulation I give some data to write into RAMs, then I read it and finally the positive reset signal to SSR pin is being sent, but after that RAMs output is still not zero...) Maybe I missed something?

 

 

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Xilinx Employee
Xilinx Employee
4,946 Views
Registered: ‎01-03-2008

Re: CoreGEN IP RAM output 0

The Virtex-4 FPGA User Guide, UG070,  describes the following behavior:

Set/Reset - SSR[A|B]

The SSR pin forces the data output latches to contain the value “SRVAL” (see “Block RAM
Attributes,” page 127). The data output latches are synchronously asserted to 0 or 1,
including the parity bit. In a 36-bit width configuration, each port has an independent
SRVAL[A|B] attribute of 36 bits. This operation does not affect RAM cells and does not
disturb write operations on the other port. Similar to the read and write operation, the
set/reset function is active only when the enable pin of the port is active. Set/reset polarity
is configurable (active High by default). This pin is not available when optional output
registers are used.

It isn't clear from your prior post if all of the conditions are met.

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