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Adventurer
Adventurer
7,604 Views
Registered: ‎05-14-2009

CoreGenerator: Problem generating DCM for Spartan-3 xc3s1000 with ISE13.2

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Hi,

 

I need to create 2 different DCMs for a project with Spartan 3 xc3s1000-5ft256.

If I use the CoreGen with ISE 13.1, In FPGA Features and design / Clocking / Spartan-3 there is a module Single DCM

version13.1.

Identifier:   xilinx.com:ip:dcm:13.1
 

Indicated as being supported for my family. The generation is OK, files are generated

 

BUT

 

When reloading the CoreGenerator, the module is eliminated and the following indicated:

 

ERROR:sim:879 - Part 'xc3s1000-5ft256' is not valid for component 'xilinx.com:ip:dcm_sp:13.1'.

WARNING:sim:863 - Failed to create component instance for XAW file 'Z:\projects\fgc\hw\pops\PAL\PAL_6M\FPGA\xproj\DCM_Slice.xaw' during project migration.

 

And is trying to compile, TRANSLATE fails with following error:

 

ERROR:NgdBuild:604: - logical block 'PAM_Clock_gen/DCM_INST2' with type 'DCM_Slice' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'DCM_Slice' is not supported in target 'spartan3'.

 

How can I generate a DCM for Spartan-3?????

 

 

PS:I have an old file (vhd) generated with Architecture Wizard (perhaps ISE 9) that is compiled correctly....

Of course I could use the same vhdl and adapt the multiplier / divider for my new cases , but .........

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Xilinx Employee
Xilinx Employee
9,803 Views
Registered: ‎01-11-2011

Re: CoreGenerator: Problem generating DCM for Spartan-3 xc3s1000 with ISE13.2

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This issue has been identified and currently there is a Change Request to have developers look into and resolve the issue. There is also more information linked below containing suggested options.

 

http://www.xilinx.com/support/answers/38170.htm

 

Please read this Answer Record for more information.

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Anonymous
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Re: CoreGenerator: Problem generating DCM for Spartan-3 xc3s1000 with ISE13.2

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Did you find a resolution to this issue?

 

I have something very similar with a Startan 6 DCM.

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Adventurer
Adventurer
7,573 Views
Registered: ‎05-14-2009

Re: CoreGenerator: Problem generating DCM for Spartan-3 xc3s1000 with ISE13.2

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Hi,

Unfortunately not... I have patched my old VHDL file instead ....

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Xilinx Employee
Xilinx Employee
9,804 Views
Registered: ‎01-11-2011

Re: CoreGenerator: Problem generating DCM for Spartan-3 xc3s1000 with ISE13.2

Jump to solution

This issue has been identified and currently there is a Change Request to have developers look into and resolve the issue. There is also more information linked below containing suggested options.

 

http://www.xilinx.com/support/answers/38170.htm

 

Please read this Answer Record for more information.

-------------------------------------------------------------------------
Please don’t forget to reply, kudo, and accept as solution!
-------------------------------------------------------------------------

View solution in original post

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Adventurer
Adventurer
7,495 Views
Registered: ‎05-14-2009

Re: CoreGenerator: Problem generating DCM for Spartan-3 xc3s1000 with ISE13.2

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Thanks

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