UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer tamas.gyorfi
Observer
4,472 Views
Registered: ‎07-23-2010

Coregen - generate simulation model only

Jump to solution

Hi,

 

I'm interested if it's possible to generate the simulation model of a core using Core Generator, without generating the netlist file.

 

Thanks in advance,

Tamas

 

0 Kudos
1 Solution

Accepted Solutions
Professor
Professor
5,520 Views
Registered: ‎08-14-2007

Re: Coregen - generate simulation model only

Jump to solution

If you only want the behavioral models, they already exist in the XilinxCoreLib library.  The structural

models are built along with the .ngc file during synthesis of the core.  The VHDL or Verilog simulation

files generated by CoreGen during customization (for behavioral models) are usually just a wrapper

around the library models.  If you generate the core once, you will find the name of the library model

in the wrapper file, and you will be able to see how the core customization was translated into

parameters (Verilog) or generics (VHDL) in the library model instantiation.  You could then edit

this file to change parameters you want until you are happy with the simulation.  Obviously if you

want to build hardware when you're done, you'll need to re-customize the core with the values

you changed, and re-generate it.

 

-- Gabor

-- Gabor

View solution in original post

0 Kudos
3 Replies
Teacher rcingham
Teacher
4,463 Views
Registered: ‎09-09-2010

Re: Coregen - generate simulation model only

Jump to solution
Why?
If you really, really, don't want the netlist file, you could always delete it off the disk...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Observer tamas.gyorfi
Observer
4,462 Views
Registered: ‎07-23-2010

Re: Coregen - generate simulation model only

Jump to solution

It would save design time when Core Generator is run only for simulation purposes.

0 Kudos
Professor
Professor
5,521 Views
Registered: ‎08-14-2007

Re: Coregen - generate simulation model only

Jump to solution

If you only want the behavioral models, they already exist in the XilinxCoreLib library.  The structural

models are built along with the .ngc file during synthesis of the core.  The VHDL or Verilog simulation

files generated by CoreGen during customization (for behavioral models) are usually just a wrapper

around the library models.  If you generate the core once, you will find the name of the library model

in the wrapper file, and you will be able to see how the core customization was translated into

parameters (Verilog) or generics (VHDL) in the library model instantiation.  You could then edit

this file to change parameters you want until you are happy with the simulation.  Obviously if you

want to build hardware when you're done, you'll need to re-customize the core with the values

you changed, and re-generate it.

 

-- Gabor

-- Gabor

View solution in original post

0 Kudos