06-02-2016 06:13 AM
I created a project to package it up as a custom IP and all of my VHDL files are set as VHDL 2008. When I package the the project up I get warnings for all of my VHDL files in the File Groups Packaging Step:
[IP_Flow 19-991] Non-synthesizable or non-simulation file 'xyz/xyz/xyz.vhd' found in file group 'Synthesis'. You may want to add it to the xit utility file group.
The type of each file is vhdlSource-2008 (auto-populated). If i change that to just vhdlSource the warning goes anyway.
I'm using Vivado 2016.1. I've built and tested the same code in project flow just fine, I'm just trying to package it up now. Any ideas?
06-02-2016 06:55 AM
Can you try to do a TOP_LEVEL of your design in VHDL (not VHDL2008)?
I think there is currently a limitation when packaging an IP with a top level in VHDL2008.
06-02-2016 07:07 AM
Thanks for the quick reply @florentw
I created a new TOP_LEVEL as just VHDL instead of VHDL2008. It's just a wrapper that instantiates my old TOP_LEVEL - I think that's what you suggested I do.
I'm still getting all the VHDL2008 related warnings. The project packages up just fine using either TOP_LEVEL. I'm just not convinced it will work or synthesize properly.
06-02-2016 07:21 AM
06-02-2016 07:44 AM
07-25-2016 06:58 AM
Push: As I can't get this to work in Vivado, even the mentioned method of adding vhdlSource-2008 (which is not in the specifcation of file types of spark 1.0, which Xilinx uses) makes the files of the IP appear as VHDL files, rather than VHDL 2008 files. (And yes I do get Syntax errors on VHDL 2008 syntax)