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Explorer
Explorer
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Registered: ‎05-16-2014

Create HDL Wrapper - Differential Signals are std_logic_vector. Want std_logic.

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When I Create an HDL Wrapper the "differential" signals are created as:

std_logic_vector(0 downto 0);

 

Is there any way to have them created as std_logic?

 

Thanks,

Swimteam

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Explorer
Explorer
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Registered: ‎05-16-2014

What if found was when instantiating the wrapper use the syntax:

refclk_p(0) => refclk;

where refclk is a std_logic;   No problems with this. I think this is better than editing the wrapper file and changing all std_logic_vectors to std_logic.

 

Swimteam

 

 

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Voyager
Voyager
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Registered: ‎03-17-2011

You can create an HDL wrapper of the generated wrapper and add it to your project source files.

--Sebastien
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Teacher
Teacher
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Registered: ‎07-09-2009

the tools are 'generic' / macro driven,

     and evidently, Xilinx are not very hot at VHDL, as they use Verilog for most things.

So the tools generate a std_logic_vector( X-1 downto 0 )

    and if X is 1, for a single bit, the tools make std_logic_vector( 0 downto 0)

 

Its a real pain. thing slike fifos that we use a lot, have single pins that are std_logic( 0 downto 0)

 

So you end up doing a lot of fred <= fred_slv;

 

where fred is std_logic and fred_slv is std_logic_vector( 0 downto  0)

 

If your using VHDL 2008, it might be worth trying type casting std_logic( fred_slv), neve rtrie dit , but its a thought

 

dont hold breath for xilxin to improve the IP, we have been on at them for decades, litraly since before ISE,

 

 

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Explorer
Explorer
350 Views
Registered: ‎05-16-2014

What if found was when instantiating the wrapper use the syntax:

refclk_p(0) => refclk;

where refclk is a std_logic;   No problems with this. I think this is better than editing the wrapper file and changing all std_logic_vectors to std_logic.

 

Swimteam

 

 

View solution in original post

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