08-24-2016 12:23 AM
I need to create Vivado design with custom IP but I need to use data size 64 bit (data width = 64 bit).
the problem encountered in my work is that Vivado design when creating an IP uses up 32-bit data size (see attached file)
So it has a solution for this problem?
Thank you very match
I wait your response
08-24-2016 02:15 AM - edited 08-24-2016 02:17 AM
This parameter is now set automatically based on the data width of whatever is driving the s2mm side of the AXI . So what you need to do is check the upstream IP and change the tdata width that it is driving out. Then the your AXI width will update accordingly.
check these document for details
08-24-2016 03:11 AM
please help me
There's a video for an example of create IP with axi lite slave datawidth=64bit?
08-31-2016 04:51 AM
Edit the customer IP in IP packager. This gives you an option to customize the parameters (like data width and address width) of the custom IP peripheral.
In this section, right click on the data width parameter and edit it as shown in below snapshot.
08-31-2016 11:32 PM
09-01-2016 10:59 AM
@smarell First you need to create as 32 bits Bus since you don't have choice in the wizard. Then you can modify AXI Interconnect Bus size by double clicking the AXI Interconnect in the Block diagram. After that enable Advance Options shown in figure below.
And in Advance Options tab you will see the Data Width of AXI Bus select the one you need!!
I hope you are looking for this. :)
09-20-2019 10:26 AM - edited 09-20-2019 10:43 AM
@smarell What if you need to integrate the block design (BD) into a top-level RTL and want to have the ability to change parameters for the BD from the RTL? Can the generated Verilog code from the IP Generator have a parameter field that can be set in the top-level RTL? Otherwise, one is forced to return to the IP Generator GUI to recustomize the IP for each different parameter setting. Perhaps this can be done via Tcl commands in non-project mode, or is there an easier way?