We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor vadim125
Registered: ‎01-31-2013

Custom AXI4 Lite switch or backup AXI4 Lite registers


I use Zynq-7030. The PS part controls a custom IP-core over AXI4-Lite interface. The IP-core uses independent clock, so I put AXI clock converter in the chain: Processor M_AXI_GP0 -> AXI Interconnect -> AXI clock converter -> PS2PL_fsm -> registers. PS2PL_fsm is a core based on Xilinx AXI4 Lite Slave template.

The problem is that clock used for the IP-core comes from an external DAC chip, so the PS must initialize it before access to the IP-core. Otherwise, the PS hangs during devmem or mmap access to the registers because there is no second clock at the AXI clock converter. Also If something happens with the DAC during operation and the clock disappears, the PS hangs as well which is not cool. I'd prefer the device try to fix this restarting the clock source or at least show an error in the web interface.

My idea was to have a backup PS2PL_fsm module working with PS clock. In case of DAC-clock failure some custom AXI4 switch tranlates all AXI transactions from normal PS2PL_fsm to the backup one. The last should just return all zeros or 32'hDEAD as AXI-data. 

I made a custom AXI4 switch IP-core with one slave and two master interfaces and put it between AXI Interconnect and AXI clock converter. It simply connects corresponding AXI wires/busses depending on external clock lock detect flag. But the tool (Vivado 2017.4) can't validate the bd:

[BD 41-703] Peripheral </axi_ps2pl_fsm_fm/S_AXI/reg0> is mapped into master segment </processing_system7_0/Data/SEG_axi_ps2pl_fsm_0_reg0>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.

What is the correct way to fix this or maybe there is some better way to prevent the PS from hanging during access to the dead axi-interface?

0 Kudos