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Adventurer
Adventurer
3,500 Views
Registered: ‎02-08-2016

Custom IP will not elaborate or synthesize when instantiated -source file type changed from Verilog to Verilog Header

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HI,

 

I generate several IP from verilog RTL. Then I re-use them in projects. I am familiar with the IP flow and concepts as explained in the documentation such as UG 1119 and UG 1118.

 

However I have a problem with several recent IPs I have generated. I can elaborate and synthesize them standalone.

 

However when I package them and then read the packages into other projects the IPs will not elaborate - the reason is that the verilog sources are shown in the project manager window as being VERILOG HEADER files not VERILOG files. Therefore the IP will not elaborate as it cannot find the modules it needs.

 

e.g.    IP "TOP"

I import the the IP and I can see 3 files :  abc.v     def.v     ghi.v   

 

IP_TOP instances module  "abc"   contained in file abc.v

module "abc" instantiates  module  "def"  defined in file def.v

module "def" instantiates module "ghi"     defined in file ghi.v

 

The trouble is that Vivado somehow changes the file type from "Verilog"   to "Verilog Header"

Therfore elaboration fails - why dos this happen??

 

Thanks Simon

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Highlighted
Adventurer
Adventurer
6,153 Views
Registered: ‎02-08-2016

 

In the Package IP there is a "packaging step"  called FILE GROUPS.  I had wrongly ticked the "Is Include" = Standard option.

 

This should only be used when a mixture of verilog and VHDL files need to be packaged for onward synthesis.

 

I ticked the "Is Include" option when it was not necessary (all files were VERILOG) and it broke

synthesis of the IP.

 

Don't do this!!!!

View solution in original post

1 Reply
Highlighted
Adventurer
Adventurer
6,154 Views
Registered: ‎02-08-2016

 

In the Package IP there is a "packaging step"  called FILE GROUPS.  I had wrongly ticked the "Is Include" = Standard option.

 

This should only be used when a mixture of verilog and VHDL files need to be packaged for onward synthesis.

 

I ticked the "Is Include" option when it was not necessary (all files were VERILOG) and it broke

synthesis of the IP.

 

Don't do this!!!!

View solution in original post