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Adventurer
Adventurer
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Registered: ‎11-06-2017

DATAWIDTH of a signal of a costum IP can not be propagated to the AXI Interconnect in Vivado 2016.3

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Hello Guys,

I have implemented an IP by Vivado HLS, and in the end modified the corresponding VHDL code in order to introduce 64-bits axi-lite registers which are accessible in one write/read. I did this, since Vivado HLS synthesizes 64-bit registers into two separeted 32-bit of access, and as a result the automatic generated driver by HLS uses two subsequent 32-bit write/read (one for 32-bit LSB and the other for 32-bit MSB), for each access to any 64-bit registers, which is desired by our requirements.

The problem is, I modified all signal width regarding those registers in generated VHDL (generated from the HLS synthesis process) into the 64-bit as well as the S_AXI_LITE interface of the IP to datawidth of 64-bit. The appearance of the IP block shows that WDATA and RDATA channels have 64-bit, but once I connect it to the PS Slave port (either automatically by Vivado or manually), the intermediate AXI Interconnect IP which is connected as a master to the slave (my costum IP) apparently can not be see the 64-bit datawidth of my custom IP.

I even removed all generated IPs source in the directory my_prj.srcs/sources_1/bd/main_design/ip/* and cleared the project cache, and revalidate the block design to let the tool repropagate the parameters across the IP blocks. Unfortunately, the problem persists eventhough the IP block of my IP shows a WDATA with 64-bit of width, by AXI Interconnect IP has got connected to that port with the datawidth of 32-bit.


I wonder if anybody has faced this problem (maybe I am doing incorrectly), and look forwared to hearing from you guys.

Cheers,
Farnam

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Adventurer
Adventurer
454 Views
Registered: ‎11-06-2017
I noticed, HLS splits a 64-bit register into the two 32-bit registers. So, to perform access, we need two times write from the software. After a long struggle, I became disappointed of HLS, finally I switched to my lovely VHDL to implement the desired registers. I hope in latest version of HLS this problem will be issued ;). Thank you.

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Adventurer
Adventurer
455 Views
Registered: ‎11-06-2017
I noticed, HLS splits a 64-bit register into the two 32-bit registers. So, to perform access, we need two times write from the software. After a long struggle, I became disappointed of HLS, finally I switched to my lovely VHDL to implement the desired registers. I hope in latest version of HLS this problem will be issued ;). Thank you.

View solution in original post

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