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Visitor nifla
Visitor
5,448 Views
Registered: ‎06-17-2011

DIFFERENCES between SOFT-HARD TEMAC

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Hy,

i have read many guides but i only understood that for the soft temac i have to buy license in order to get hold of source code, whereas hard temac is available as a ready to use core, in EDK and coregen.

 

Are there other PRACTICAL differences between soft and hard temac?

 

Thanks in advance!

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Xilinx Employee
Xilinx Employee
6,839 Views
Registered: ‎09-24-2007

Re: DIFFERENCES between SOFT-HARD TEMAC

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They are very different!  "soft" means imlemented in the FPGA fabric gates like other "soft" IP, and requires timing and placement integration with all of your other FPGA "soft" logic.  "Hard" means implemented as a fixed ASIC core embedded in the FPGA fabric, similar to BRAM or DSP48 blocks.  Because of this, the Coregen cores are different, are maintained under different rev. and device control, and cannot be substituted for each other.  Typically, the source code is not delivered with the "soft" core, only an encrypted compiled net list.

 

On the other hand, the two cores are functionally very similar, and both will serve most of the requirements for a TEMAC.  If the FPGA that you choose has the TEMAC as a "hard" core, then you will not need to pay for the license, although a license may still be required.  If you pick a device with "hard" cores and use them all, you can still add more "soft" cores.  There are many Answer Records on Xilinx Support which explain the feature sets etc. of the various MAC TEMAC cores available.

Regahds
3 Replies
Xilinx Employee
Xilinx Employee
6,840 Views
Registered: ‎09-24-2007

Re: DIFFERENCES between SOFT-HARD TEMAC

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They are very different!  "soft" means imlemented in the FPGA fabric gates like other "soft" IP, and requires timing and placement integration with all of your other FPGA "soft" logic.  "Hard" means implemented as a fixed ASIC core embedded in the FPGA fabric, similar to BRAM or DSP48 blocks.  Because of this, the Coregen cores are different, are maintained under different rev. and device control, and cannot be substituted for each other.  Typically, the source code is not delivered with the "soft" core, only an encrypted compiled net list.

 

On the other hand, the two cores are functionally very similar, and both will serve most of the requirements for a TEMAC.  If the FPGA that you choose has the TEMAC as a "hard" core, then you will not need to pay for the license, although a license may still be required.  If you pick a device with "hard" cores and use them all, you can still add more "soft" cores.  There are many Answer Records on Xilinx Support which explain the feature sets etc. of the various MAC TEMAC cores available.

Regahds
Xilinx Employee
Xilinx Employee
5,435 Views
Registered: ‎08-13-2007

Re: DIFFERENCES between SOFT-HARD TEMAC

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Very good input above.

 

From a practical perspective, the hard TEMAC are only available on certain families (V4FX, V5, V6), exist is fixed quantities, and don't require a $ license. Note they do not exist on the 7 series parts - most likely because the soft TEMAC is pretty small and it is impossible to satisfy every application. Many applications didn't use them, some used only part of them, and others required more and had to supplement with additional soft TEMACs.

 

From a functional perspctive, they are all very similar. For the complete list, see the respective user guides.

But here is a fairly concise list of similarities/differences that might be useful:

 

Soft Tri-mode EMAC for all Virtex and Spartan family devices
 Runs up to 1Gbps
 1000BASE-X or SGMII support is achieved through separate 1000BASE-X or SGMII core
 Half Duplex support at all rates
 Statistics are delivered in a parallel vector
 Supports configurable number of address table entries (1-4 tables)
 Slight differences in registers since PHY info is not available
 No DCR support

 

 

Embedded Tri-mode EMAC for Virtex-6, Virtex-5 & Virtex-4
 Virtex-6 runs at 2.5 Gbps
 1000BASE-X or SGMII built-in
 No Half Duplex support at 1 Gbps
 Stats are delivered serially
 Ethernet Statistics core can interface directly to this serial interface
 Supports 0, 1, 2, 3, or 4 address table entries
 Slight differences in registers since PHY info is available

 


Virtex-5 TEMAC
Supports legacy Virtex-4 FX FPGA feature set
 Standard PHY interface support
  MII, GMII, RGMII, SGMII
  PCS/PMA for 1000BASE-X
 Selectable host interface
  Generic host or DCR host
 Receive address filter
 Jumbo-frame support
  Increased bandwidth with larger packets
  Reduced host processing
 Network traffic monitoring and filtering
  Real time statistics for Tx / Rx
Enhanced interfaces and features
 Reduces number of clock resources
 Increases flexibility for processor and serial interfaces
 Flexible Auto-Negotiation
  Programmable timer select to optimize link connection
  Minimizes processing time overhead for interrupts
  Reduces simulation time
 Unidirectional mode
  Supports Unidirectional enable function – required by IEEE802.3ah-2004
  Enables EMAC to transmit when invalid input is present at the receiver
 Loopback in EMAC core and in the transceiver
  Improved debug capability over Tx / Rx datapath on PHY interface
  Ensures that link remains active by transmitting idles to the link partner
 Reduced number of clocking resources
  Advanced clocking support
  Enables 50% reduced clocking resources in MII, GMII, RGMII modes

 

 

Virtex-6 TEMAC
Supports legacy Virtex-5 FX FPGA feature set:
 Standard PHY interface support
  MII, GMII, RGMII, SGMII
  PCS/PMA for 1000BASE-X
 Selectable host interface
  Generic or Dynamic Configuration host (DCR)
 Receive EMAC address filter
 Jumbo-frame support
  Increased bandwidth with larger packets
  Reduced host processing
 Network traffic monitoring and filtering
  Real time statistics for Tx / Rx
 Up to four blocks per device
New features
 New over-clocking feature
  Full support for over-clocking to 2.5 Gbps (1000BASE-X only)
  Not an IEEE standard but supported by many 3rd party IC vendors.
 Single core per TEMAC block
  No more sharing DCR and Host buses like in Virtex-5
  Simplified architecture, individual clocking resources
  Reduced size of the wrapper file
  Simplified menu in tool wizards (Coregen)
 New statistic feature
  New address match signal available to the fabric
  Allows to build more accurate statistic engine

 

 

 

Cheers,

bt

 

 

Visitor nifla
Visitor
5,417 Views
Registered: ‎06-17-2011

Re: DIFFERENCES between SOFT-HARD TEMAC

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Thanks!You've been very helpful! :)

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