cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
efpkopin
Adventurer
Adventurer
380 Views
Registered: ‎01-20-2017

Defining open drain SDA signal in I2C peripheral within a custom IP

Jump to solution

I have a custom IP with an included I2C peripheral (aka 'slave') that I use as part of a larger project in a Vivado Block Diagram design.  Accordingly, there are three SDA signal ports ((input) SDA_I, (output) SDA_O and (output) SDA_T) defined in my custom IPs I2C interface.  When I package my custom IP (in the IP Packager interface), on the 'Ports and Interfaces' tab, I have been adding a 'gpio_rtl' (General purpose input output interface) and mapping the above three signals to that interface in my custom IP.  This way, I can bring this I/O signal from my custom IP to an external port of the top level design.  Then when I create an HDL Wrapper (and let Vivado manage the process), it instantiates an IOBUF for these three signals as needed.

My primary question is, if I bring these three signals out to the top level in this way, do I also have to infer SDA_O as an open drain in the I2C VHDL code (w/in my custom IP) using the line of code:

 

SDA_O <= 'Z' when SDA_T = '1' else '0';

 

Or is it redundant to include both this line of VHDL code (in the custom I2C interface) along with the IOBUF at the top level of my project?

 

 

0 Kudos
1 Solution

Accepted Solutions
drjohnsmith
Teacher
Teacher
311 Views
Registered: ‎07-09-2009

Xilinx FPGA do not support open drain, internal or external, 

    as you have done is the correct way to make an equivalent for an IO pin

 

Inside the FPGA , you only have uni direction signlals,

 

so assuming SDA_0 is your pin

 

in your code, when you want to "read" the pin you use

foobar <= SDA_0;

when you what to output you use

SDA_0 <= my_signal;

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

1 Reply
drjohnsmith
Teacher
Teacher
312 Views
Registered: ‎07-09-2009

Xilinx FPGA do not support open drain, internal or external, 

    as you have done is the correct way to make an equivalent for an IO pin

 

Inside the FPGA , you only have uni direction signlals,

 

so assuming SDA_0 is your pin

 

in your code, when you want to "read" the pin you use

foobar <= SDA_0;

when you what to output you use

SDA_0 <= my_signal;

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post