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Explorer
Explorer
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Registered: ‎10-27-2013

Differential LVDS termination in clock wizard

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I ma using Vivado 19.2 & Artix 7. My clock source to FPGA is LVDS_25 differential signal.

I want to connect this clock to a clock wizard with differential input pin setting How to enable DIFF_TERM termination in this scenario.

As of now i apply the signals as the following


clk1 : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
port map (
O => clk,
I => clk_p,
IB => clk_n
);

 

so if i connect clk to clock wizard (No buffer) input I guess no BUFG need to connect to clock wizard. Or do I??

 

 

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236 Views
Registered: ‎01-22-2015

Re: Differential LVDS termination in clock wizard

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@marcb  &  @rakeshm55 

Sorry for jumping in here, but I think the solution is:

  1. Ensure clock enters Artix-7 on clock capable pin-pair (let's give them port names, CLKP, CLKN)
  2. Do not instantiate IBUFDS in your design (because Clocking Wizard will automatically do that for you).
  3. In Clocking Wizard, indicate that Input Clock "Source" is "Differential clock capable pin"
    clock_wiz_diff_input.jpg
  4. In Vivado .xdc constraints file, add a constraint like the following to turn-on the internal termination of IBUFDS for the LVDS clock input.
    set_property DIFF_TERM TRUE [get_ports CLKP] 

 

The resulting connections will be:

clock-in  >  pins(CLKP,CLKN)  >  IBUFDS  >  clock-dedicated-route  >  MMCM  >  BUFG > clock(s)-out

Cheers,
Mark

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4 Replies
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Differential LVDS termination in clock wizard

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Hi @rakeshm55 

I would expect that you would still need a BUFG instantiation in this case. The IBUFG* type of buffers originally targeted earlier architectures in which a BUFG was inserted. However, for new architectures, a separate BUFG instantiation is needed with the use of a IBUFG* buffer type.

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Explorer
Explorer
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Registered: ‎10-27-2013

Re: Differential LVDS termination in clock wizard

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1. What about using differential clock pins enable in clock wizard directly with termination enabled??

2. In 2nd case

 

IBUFDS ------> BUFG ----> CLk Wizard ----> BUFG -----> out_clk

Why a separate BUFG needed for clk Wizard input if the clock not used any where else??

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Differential LVDS termination in clock wizard

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Hi @rakeshm55 

The DIFF_TERM should have nothing to do with BUFG insertion. I do not have the history behind the need for a BUFG when an IBUFG is used, but this has been the expected behavior for the last few architectures. The IBUFG* is not listed in the Vivado version of the Libraries Guide, but is in the ISE version. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug953-vivado-7series-libraries.pdf

 

I'm not sure if I am fully following your question. If you are asking about the Clocking Wizard options related to using both clock inputs, maybe posting the XCI would help. I have been speaking to the synthesis behavior of BUFG insertion related to the IBUFDS primitive.

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
0 Kudos
Highlighted
237 Views
Registered: ‎01-22-2015

Re: Differential LVDS termination in clock wizard

Jump to solution

@marcb  &  @rakeshm55 

Sorry for jumping in here, but I think the solution is:

  1. Ensure clock enters Artix-7 on clock capable pin-pair (let's give them port names, CLKP, CLKN)
  2. Do not instantiate IBUFDS in your design (because Clocking Wizard will automatically do that for you).
  3. In Clocking Wizard, indicate that Input Clock "Source" is "Differential clock capable pin"
    clock_wiz_diff_input.jpg
  4. In Vivado .xdc constraints file, add a constraint like the following to turn-on the internal termination of IBUFDS for the LVDS clock input.
    set_property DIFF_TERM TRUE [get_ports CLKP] 

 

The resulting connections will be:

clock-in  >  pins(CLKP,CLKN)  >  IBUFDS  >  clock-dedicated-route  >  MMCM  >  BUFG > clock(s)-out

Cheers,
Mark

View solution in original post