04-18-2015 08:10 PM
Hi am new here I may be posting this in the wrong forum. My background is I used ISE 10 but mainly used the schematic capture and the FSM software for my designs. I used a little VHDL and Verilog from the library to form some blocks for my schematic projects. For the most part my designs have all centered around Schematics. I have some unique design blocks for full projects I did with the finite State machine software. I have in stock has a board with a Spartan 3500E on it and I was planning to use for a demo when I found out this board is being discontinued. The new board of the same series has a 7A100 in it. This will multiply my capabilities compared the old board I had. I also downloaded the Vivado series design tool and found it very powerful in some aspects to ISE. I lost my connection to someone that can write code and Tcl script. I need to get this demonstration model done ASAP so I have the following questions.
04-19-2015 08:11 AM
Vivado is for 7 series an newer. It does not (will not) support anything older.
ISE 14.7 ISE is the last ISE for all older products, and is supported. You may have to use it on a Linux/Unix machine (real or virtual), as using ISE on new Windows versions may be (probably is) dificult. Tlak to you Xilinx or Avnet FAE if you have problems with ISE 14.7 on your machines (or post here).
I found Vivado a wonderful environment, after using the older tools (I have used Xilinx tools since 1985).
Schematics are not really useful any longer as the designs are far too large (schematics become unwieldy).
I suggest you download Vivado, and go to work.
Older designs may be exported from ISE so that they may be inpt to Vivado as RTL code.
Packaging modules as library IP blocks in Vivado, and managing them is cleaner and easier.
Of course, I have a bias here (Xilinx customer since 1985, and Xilinx employee since 1998.
04-20-2015 05:53 AM
Some more points:
It is possible to target the XC7A100T with the latest version of ISE (14.7i) if you don't want to migrate to Vivado at this time.
Sometime after ISE 10, the FSM generator (StateCAD? I forget the name of it...) was removed from ISE, but you can still use the Verilog or VHDL it generates in any newer tool set.
Xilinx support for schematic-based design has been pretty bad since they dropped the Aldec front-end and created ISE. Vivado has a block design flow that might be of interest, but I haven't tried it myself.
Xilinx seems to have a general dislike for graphics-based design entry. I think this may be because they haven't actually had the resources to develop it properly and their main focus is on getting the back-end tools to work well (making the design run efficiently on their parts). At each point when their tool chan was revamped, they left any schematic-based design stranded with the old tools (no upgrade path). This has led a lot of people who prefer schematics, usually for the top level of a design, to abandon it entirely or move to third-party tools like those from Aldec.