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Explorer
Explorer
1,895 Views
Registered: ‎11-01-2015

Does IPI support modules using VHDL2008?

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Hi ,

As far as I know, IPI can support 'Add Module to Block Design', but if the module is described by VHDL 2008, IPI will fail to support.

So when will IPI support VHDL 2008 or System Verilog?

 

Thanks,

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Scholar
Scholar
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Registered: ‎04-26-2012

@howardp  "VHDL 2008 modules can be used under module reference but just not as the top level HDL of the module reference."

 

This statement contradicts the IP packager documentation found in UG1118:

UG1118-VHDL2008.png

 

It would seem strange that one could use non-top-level VHDL-2008 for module references as stated in UG994, but not for packaged IP as stated in UG1118.

 

-Brian

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-22-2008

SystemVerilog and VHDL 2008 modules can be used under module reference but just not as the top level HDL of the module reference.  See TIP on page 216 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug994-vivado-ip-subsystems.pdf.

 

When will VHDL 2008 be able to be added as the top level HDL of a module reference block in IPI?  I do not know the answer and don't expect to know until I actually see it supported in a release build of the software.  I do know that it is on the schedule, and part of the work has been done but it will not be enabled in a production release until it is robust enough to support a good set of VHDL2008 code. 

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Scholar
Scholar
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Registered: ‎04-26-2012

@howardp  "VHDL 2008 modules can be used under module reference but just not as the top level HDL of the module reference."

 

This statement contradicts the IP packager documentation found in UG1118:

UG1118-VHDL2008.png

 

It would seem strange that one could use non-top-level VHDL-2008 for module references as stated in UG994, but not for packaged IP as stated in UG1118.

 

-Brian

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-22-2008

It is not a contradiction at all.  As you noted, UG1118 is referring to IP Packager and UG994 is referring to Module Reference.

The biggest difference that I see is that a module reference file been explicitly added and can be defined as a VHDL 2008 type file in the current project.

IP Packager and Module Reference do have the same (or at least similar) problem with regards to top level VHDL 2008 support in that they cannot reliably ascertain the correct port/pin definitions.

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Scholar
Scholar
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Registered: ‎04-26-2012

@howardp   "It is not a contradiction at all.  As you noted, UG1118 is referring to IP Packager and UG994 is referring to Module Reference."

 

Perhaps 'contradiction' wasn't the best word- but it certainly seems odd that IP Integrator would allow one and not the other.

 

Let me rephrase: to your knowledge, one still can can not use *any* VHDL-2008 in the 2018.1 IP packager flow, correct?

 

-Brian

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-22-2008

Correct.  From my understanding, one still can not use *any* VHDL-2008 specific HDL in the 2018.1 IP packager flow.

 

From what I've seen, someone can package a project that contains VHDL-2008 modules in a lower level and those files will get added to the user IP and will be delivered with the output products of the IP core at generation.  However, they will be delivered as files of the synthesis file group (or other applicable file group(s)) but, at that point there will be no designation file type.  Therefore, they will be interpreted as VHDL based on the file extension.

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Moderator
Moderator
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Registered: ‎06-14-2010

Hello @araongao2015,

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 

 

If this is not solved/answered, please reply in the thread.

 

Thanks in advance and have a great day.

 

 

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Scholar
Scholar
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Registered: ‎06-10-2008

@howardp wrote:

Therefore, they will be interpreted as VHDL based on the file extension.


Not related to IPI, but generic Vivado:

In Vivado 2018.2 I noticed when I tried to add files, I could choose <all files> or <VHDL 2008> files. But it stays a mistery what file extension it searches for. It certainly isn't .vhd as those stay hidden.

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