04-09-2016 01:58 PM
is it possible to double an AXI stream?
I have an output from an IP Core. This one goes to a AXI4-Register Slice. This AXI stream contains the important values tready and tvalid. I need them. I'd like to put for example tvalid to an output pin to see when something is written and the time between writings. Is it possible to "duplicate" the AXI stream to get the data on one of them? If yes, how? I hope my aim is clear.
04-09-2016 02:18 PM
If you can change the source for your IP core this should be pretty trivial. Just make an extra observer AXIS port and ignore the ready input from it. If your design is HDL source you can just take the signals and wire them to your observer IP. Otherwise you probably need to write an IP (that wouldnt have an logic, just define the AXIS splitter wiring).
04-10-2016 02:04 AM
im not sure if I understand you correctly.
This is my AXI stream. And I'd like to know when something is written and when it is not. So I'd like to get the TVALID value to an output pmod port to see the writings with an oscilloscope. So what exactly do I have to do to get the value? The image_filter core is made with HLS, and there a typical AXI_STREAM is used. How to get the data now :/
04-10-2016 02:24 AM
So you don't have RTL access.
You problem sounds similar to using chipscope which supports spying on an AXI bus. I just had a play around with the block diagram, and it looks like the chipscope ILA supports AXI stream. So instead of pinning to a PMOD you can use chipscope to see your information.
In block diagram add the ILA IP. In Monitor Interface 0 tab change protocol to AXI4S from there, you should be able to connect the ILA port as a third party to your existing connection.
04-10-2016 02:56 AM
im not sure if it works with an ILA. The whole bitstream is put on a petalinux and used by sdk functions. I dont think that I can have access to the ILA analyzer then.
Are there any other ways to get to know when something is written there?
thanks for your reply
04-10-2016 02:59 AM
ILA is implemented in hardware and accessed over the JTAG. So you can use it completely indepedently of software. You can even use your target software to trigger some event and watch it on the logic analyzer. Its not uncommon to run a script in linux and have that trigger the logic analyzer.
Even if the software stack is loading the bitstream, chipscope should be able to connect after the load.
04-10-2016 03:09 AM - edited 04-10-2016 03:18 AM
Just to get it right:
When I use the function on the petalinux, i connect the jtag to the pc and open the hardware manager in vivado, then open target -> search for the zc702 and then it should automatically detect that the bitstream is already written on it and ila is used, so i can use the ila logic analyzer there?
thank you very much
04-10-2016 03:21 AM
Its been a while since I have done it so im hazy on the chipscope toolflow. Chipscope was its own program separate from ISE. But if by "function on the petalinux" you mean the software bitstream loader, then the order of steps sounds right. I assume you have your own function after that that you can kick, that will start the traffic you are interested in.
04-10-2016 03:25 AM
All I remember from my ILA experience is that after I load the FPGA with JTAG the ILA analyzer opens inside Vivado. No other software.
But now i programm the petalinux with an sd card, and then run a shell which configures the PS to do the things i want to do. There I need to use the ILA and see what is going on and when something is written.
Can I use the Vivado ILA analyzer then and how?