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baltintop
Voyager
Voyager
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Registered: ‎06-28-2018

ERROR: [Common 17-69] Command failed: The current design is not implemented.

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Hello,

When I generate a bitstream and try to export hardware including the bitstream I get an error message stating that the design is not implemented. When I close and reopen Vivado I can export the hardware without any issue. What causes this error? Is there a way to solve this without closing Vivado?

I am using Vivado version 2019.2 on Ubuntu 18.04. The following is the TCL console output.

write_hw_platform -fixed -force  -include_bit -file /path_to_vivado_project/top_module.xsa
INFO: [Vivado 12-4895] Creating Hardware Platform: /path_to_vivado_project/top_module.xsa ...
Command: write_bitstream -force ~/.Xil/Vivado-some_number-motherboard_model/xsa_6/top_module.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.

Evaluation cores found in this design:
    IP core 'pl_eth_sgmii_xilinx_mac_tri_mode_ethernet_mac_0_0' (pl_eth_sgmii_xilinx_mac_tri_mode_ethernet_mac_0_0_block) was generated with multiple features:
        IP feature 'eth_avb_endpoint@2015.04' was enabled using a design_linking license.
        IP feature 'tri_mode_eth_mac@2015.04' was enabled using a hardware_evaluation license.

Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
INFO: [Common 17-83] Releasing license: Implementation
3 Infos, 0 Warnings, 1 Critical Warnings and 1 Errors encountered.
write_bitstream failed
ERROR: [Common 17-69] Command failed: The current design is not implemented.
ERROR: [Common 17-69] Command failed: ERROR: [Common 17-69] Command failed: The current design is not implemented.

Thanks.

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1 Solution

Accepted Solutions
syedz
Moderator
Moderator
2,720 Views
Registered: ‎01-16-2013

@ugarro @Jonas_C  @olebon @baltintop 

 

Please share the Vivado.log file and Vivado.jou file of the failing project? Can you try using any of the Xilinx IPI example designs and check? (File-->Project-->Open Example...)

Do you see any fixed pattern in getting this error? If yes, please share it to reproduce it at our end.

I have tried this on my machine using 2019.2 but I do not get the error. 

Under Flow Navigator, If you have clicked on "Run Implementation" then Make sure you open the implemented design and then generate xsa file (File-->Export-->Export Hardware..)

launch_runs impl_1 -jobs 12
open_run impl_1
write_hw_platform -fixed -force -include_bit -file C:/project_3/base_zynq_wrapper.xsa

If you have clicked on "Generate Bitstream" then you can generate the xsa file without opening the implemented design:

launch_runs impl_1 -to_step write_bitstream -jobs 12
write_hw_platform -fixed -force -include_bit -file C:/project_3/base_zynq_wrapper.xsa

 

Note: Ubuntu 20.04 is not supported with Vivado 2019.2. Link

 

--Syed

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16 Replies
graces
Moderator
Moderator
3,270 Views
Registered: ‎07-16-2008

When you proceeded with bitstream generation but it complained about "the currrent design is not implemented", did you actually finish implementation and implementation status is complete?

 

 

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baltintop
Voyager
Voyager
3,263 Views
Registered: ‎06-28-2018

Hi @graces 

Yes, the implementation had finished successfully. When I reopened Vivado I could directly export the hardware without running anything. I get this error message for certain projects even though I cleaned all the residual/temporary files and re-implemented the design.

Thanks.

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graces
Moderator
Moderator
3,257 Views
Registered: ‎07-16-2008

The error is in write_bitstream phase, rather than exporting hardware. When you re-open the project, can you succeed in bitstream generation?

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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baltintop
Voyager
Voyager
3,249 Views
Registered: ‎06-28-2018

Hi @graces 

I forgot to mention that bitstream generation also finishes successfully and the exported hardware includes the bitstream. I never tried running bitstream generation after reopening Vivado because I never needed to.

Thanks.

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baltintop
Voyager
Voyager
3,236 Views
Registered: ‎06-28-2018

Looks like the issue is resolved, I no longer receive that error message.

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baltintop
Voyager
Voyager
3,151 Views
Registered: ‎06-28-2018

The issue persists. It seems that this happens only if the implemented design contains ILA cores.

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olebon
Observer
Observer
2,954 Views
Registered: ‎05-10-2019

I just also had the same issue and it is also intermittent. Closing and reopening the project helps, but sometimes the issue comes back. In my case it stared after saving the project under a different name.

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Jonas_C
Visitor
Visitor
2,799 Views
Registered: ‎05-10-2020

The same problem when executing Export Hardware,
But after restarting Vivado, it's no problem,
My operating environment is Win10 with Vivado 2019.2.

Does anyone know why?

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ugarro
Visitor
Visitor
2,737 Views
Registered: ‎05-06-2018

I can confirm the same issue here, on Vivado 2019.2 inubuntu 20.04. Implementation correctly done, but fails with that message when exporting the bitstream.

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syedz
Moderator
Moderator
2,721 Views
Registered: ‎01-16-2013

@ugarro @Jonas_C  @olebon @baltintop 

 

Please share the Vivado.log file and Vivado.jou file of the failing project? Can you try using any of the Xilinx IPI example designs and check? (File-->Project-->Open Example...)

Do you see any fixed pattern in getting this error? If yes, please share it to reproduce it at our end.

I have tried this on my machine using 2019.2 but I do not get the error. 

Under Flow Navigator, If you have clicked on "Run Implementation" then Make sure you open the implemented design and then generate xsa file (File-->Export-->Export Hardware..)

launch_runs impl_1 -jobs 12
open_run impl_1
write_hw_platform -fixed -force -include_bit -file C:/project_3/base_zynq_wrapper.xsa

If you have clicked on "Generate Bitstream" then you can generate the xsa file without opening the implemented design:

launch_runs impl_1 -to_step write_bitstream -jobs 12
write_hw_platform -fixed -force -include_bit -file C:/project_3/base_zynq_wrapper.xsa

 

Note: Ubuntu 20.04 is not supported with Vivado 2019.2. Link

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

syedz
Moderator
Moderator
2,552 Views
Registered: ‎01-16-2013

@baltintop 

 

Did the above information from my previous post was helpful? Let us know if you are still stuck with the error. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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baltintop
Voyager
Voyager
2,547 Views
Registered: ‎06-28-2018

Hi @syedz 

I no longer have access to that particular project but I've accepted your answer as solution.

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ugarro
Visitor
Visitor
2,445 Views
Registered: ‎05-06-2018

@syedz ,  sorry for the late response. I could not reproduce it in the last few times.

I just now had this issue again, so I tried your  suggestions.  As I had clicked on generate bitstream, first I tried to export the bitstream:

launch_runs impl_1 -to_step write_bitstream -jobs 12
ERROR: [Vivado 12-978] Step 'write_bitstream' is already run and up to date.

And exporting the .xsa worked just fine:

write_hw_platform -fixed -force -include_bit -file /home/ugarro/foo.xsa

INFO: [Vivado 12-4895] Creating Hardware Platform: /home/ugarro/foo.xsa ...
INFO: [Vivado 12-4896] Successfully created Hardware Platform: /home/ugarro/foo.xsa
write_hw_platform: Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 10110.617 ; gain = 7.000 ; free physical = 562 ; free virtual = 12514

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zhengk98
Newbie
Newbie
1,633 Views
Registered: ‎11-01-2020

I also met this error. And I find that if the bitfile exists under the directory exported by xsa file, this error will disappear~

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olupj
Explorer
Explorer
1,366 Views
Registered: ‎01-27-2008

I am getting this failure and I have an ILA (although able to export with ILA previously).

I tried this technique, which I believe is export the XSA to the impl_N directory (adjacent to the bitstream). It fails.

Fortunately the processor architecture didn't change and I just moved the bitstream to the platform directory ... for now, ok but definitely an issue @syedz.

 

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tamas.kiss
Contributor
Contributor
682 Views
Registered: ‎04-30-2019

I ran into the same problem when an out-of-date synthesized design was opened in the background. Closing/refreshing it solved it for me.

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