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jmperez0
Newbie
Newbie
464 Views
Registered: ‎04-08-2019

ERROR: [Synth 8-6032] unexpected vhdl node type '%s'

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Hi,

In Vivado 2020.1 I'm getting error [Synth 8-6032] on the following VHDL 20008 code:

 

package p is
	generic (n : natural);
	
	subtype t is natural range 0 to n-1;
end package;

package body p is
end package body;


library ieee;
use ieee.std_logic_1164.std_logic;

entity generic_bug is
	generic (n : natural);
	port(signal dummy : in std_logic);
end generic_bug;


library ieee;
use ieee.std_logic_1164.std_ulogic_vector;

architecture beh of generic_bug is
	package pkg is new work.p
		generic map (n => n);
	
	signal s : std_ulogic_vector (pkg.t); -- pkg.t seems to trigger Synth 8-6032
begin
end beh;


entity top is
end entity;


library ieee;
use ieee.std_logic_1164.std_logic;

architecture beh of top is
begin
	e : entity work.generic_bug
		generic map (n => 3)
		port map (dummy => '0');
end beh;

Is this case unsupported? Thanks in advance.

 

 

 

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pulim
Xilinx Employee
Xilinx Employee
444 Views
Registered: ‎02-16-2014

Hi @jmperez0 

 

This seems to be issue which is not yet supported.I reported this issue to get it fixed.

You can declare subtype in architecture as below and use as workaround to move forward with your design.

subtype t1 is natural range 0 to n-1;
 signal s : std_ulogic_vector (t1);

 

Thanks

Manusha

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pulim
Xilinx Employee
Xilinx Employee
445 Views
Registered: ‎02-16-2014

Hi @jmperez0 

 

This seems to be issue which is not yet supported.I reported this issue to get it fixed.

You can declare subtype in architecture as below and use as workaround to move forward with your design.

subtype t1 is natural range 0 to n-1;
 signal s : std_ulogic_vector (t1);

 

Thanks

Manusha

View solution in original post

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