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Visitor
Visitor
1,958 Views
Registered: ‎08-08-2018

ERROR: [filemgmt 56-189] Failed to resolve reference. Nothing was found in the project to match the name 'aud_pat_gen'

ERROR: [filemgmt 56-189] Failed to resolve reference. Nothing was found in the project to match the name 'aud_pat_gen'.
ERROR: [Runs 36-346] File '_1/bd/design_vu440/ip/design_vu440_aud_pat_gen_0/design_vu440_aud_pat_gen_0.xci' needed for run contains invalid reference(s).

 

I took a working .bd design for the KCU105 and targeted a new device VU440.

Manually created all the blocks and now I get this error when I Run Synthesis.

 

I tried to WA it by adding the .xci for this block under PROJECT MANAGER -> Settings -> Add Sources.  But got the same error.

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Moderator
Moderator
1,883 Views
Registered: ‎09-15-2016

Hi @dtokhi,

 

You can check if the IPs are re targeted for the new part changed > report_ip_status -name ip_status.

 

Thanks

Prathik

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Contributor
Contributor
1,020 Views
Registered: ‎06-24-2019

Hi, I have the same problem,and I tried the tcl command to check the ip_status, it showed that "Module reference is unresolved", and I found in the source Hierarchy, there is a question icon before the module, it means the verilog file is missing while I tried to add the file, it prompts a warning that "WARNING: [filemgmt 56-12] File 'xxxx.v' cannot be added to the project because it already exists in the project, skipping this file". But the missing icon is still there, how can solve it? Thanks.

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