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Explorer
Explorer
615 Views
Registered: ‎12-08-2007

Edit IP Parameter

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I am using Vivado v2018.3 

I am learning how to create an IP. I am following UggFPW-xup_building_basic_elements_lab.pdf which has Verilog examples. I am interested in doing this in VHDL.

So I create VHDL code of an AND gate with a DELAY parameter as follows:

entity and2 is
generic (DELAY: time);
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           y : out STD_LOGIC);
end and2;

architecture Behavioral of and2 is

begin

y<= a and b after DELAY ;

end Behavioral;

Then I do "Create and Package new IP", and in the section"Customization Parameters" I edit the DELAY parameter. but there is no type Time. I only see the types : long, float, bool, .... See attached.

 

If I choose long, then later when I create a repository and I add this AND gate into my block design, when I try to "Generate Output Products" I get an error message: 

 

ERROR: [IP_Flow 19-3286] Unsupported VHDL data type 'TIME' for long value.
ERROR: [IP_Flow 19-154] Failed to convert long value '0' to HDL value.
ERROR: [IP_Flow 19-3814] Failed to get HDL value for model parameter 'DELAY'.

How is it possible to have a parameter which acts as value for a delay (in VHDL)?

 

 

Screen Shot 2020-03-17 at 22.30.24.png
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Xilinx Employee
Xilinx Employee
446 Views
Registered: ‎10-01-2007

Try

-- synthesis translate_off

...Code to be ignored...

-- synthesis translate_on

View solution in original post

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8 Replies
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Xilinx Employee
Xilinx Employee
567 Views
Registered: ‎10-01-2007

IP Packager is for synthesis so time wouldn't make sense.  You can obviously do that for simulation.  But not synthesis.

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Explorer
Explorer
560 Views
Registered: ‎12-08-2007

But the document 

Buidling Basic Elements for IPI

in UggFPW-xup_building_basic_elements_lab.PDF

does this in Verilog and then runs a TEST BENCH and one can see the DELAY in the simulation waveforms.

So the IP created (in Verilog) has DELAY which is interpreted in the simulation, not just synthesis

(I'm unfamiliar with Verilog, is time delay in Verilog done in 'long' type (in contrast to 'time' type in VHDL) ?)

 

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Xilinx Employee
Xilinx Employee
558 Views
Registered: ‎10-01-2007

Yes you can have that parameter in your IP for simulation.  The packager customization GUI won't parse it since it is passing parameters for synthesis.

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Explorer
Explorer
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Registered: ‎12-08-2007

The code in Verilog:

`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////
// Module Name: xup_and2
/////////////////////////////////////////////////////////////////
module xup_and2 #(parameter DELAY=3)(
input a,
input b,
output y
);

and #DELAY (y, a, b);

endmodule

And this works with the IP creator and runs in Simulation when I create a system which has this as an IP.

 

What would I have to write  in VHDL in order for the simulation to work?

I tried, 

 

 

ntity and2 is
generic (DELAY: time);
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           y : out STD_LOGIC);
end and2;

architecture Behavioral of and2 is

begin

y<= a and b after DELAY ;

end Behavioral;

but as I wrote earlier, it does not work

 

 

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Explorer
Explorer
452 Views
Registered: ‎12-08-2007

Any update on this?  Still waiting for a response.  There has to be a way to do this

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Highlighted
Xilinx Employee
Xilinx Employee
447 Views
Registered: ‎10-01-2007

Try

-- synthesis translate_off

...Code to be ignored...

-- synthesis translate_on

View solution in original post

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Highlighted
Explorer
Explorer
396 Views
Registered: ‎12-08-2007

Thanks for your reply.

I managed to solve the error this way (I'm not sure if this is the most elegant way of doing it).

entity and_gate is
generic (delay: integer range 0 to 20); -- I choose integer instead of type time since IP packger does not accept time for parameter
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           y : out STD_LOGIC);
end and_gate;

architecture Behavioral_1 of and_gate is

begin


    y<= 'W'; -- I just plan to run simulation of this AND gate and resolution function
-- of std_logic ensures that anything in contention with 'W' remains as is. -- synthesis translate off y<= a and b after 1 ns * delay; -- this is seen only by simulator and not synthesis -- synthesis translate_on end Behavioral_1;

and then I create an IP from this AND gate, I choose import the parameters from the HDL file. And I see that it chooses for parameter delay the type long and reads the range 0 to 20. I select default value.

Then I create another project with another system, using block design. I add the above AND gate several times, choosing different values of the DELAY parameter.

There is on error now when I create the wrapper for the system. I then write Test Bench and simulate the system and I can see the delay working.

 

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Xilinx Employee
Xilinx Employee
341 Views
Registered: ‎10-01-2007

The packager can certainly accept an integer value but synthesis can't process delay statements so the translate_off is the way to do it.  Did you say you are still getting an error?  What error if so?

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