I posted this back in Dec. but never got a response...maybe my subject line wasn't interesting enough... :)
I have been working on a design (both in Xilinx and...sorrry to say...Lattice Semi). What I am trying to do is edit symbols for aesthetics and keeping the designs a bit more compact. All I am really changing is the shape of the device, moving pins around as needed, and for those devices where the pin label is external, I am moving it inside the box, so to speak.
When I go to "compile" the design, everything seems to work fine up thru the synthesize step. When I get to translate, I get somewhere in the neighborhood of 25 errors of the following format:
ERROR:NgdBuild:604 - logical block 'XLXI_55' with type 'X74_138_MXILINX' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'X74_138_MXILINX' is not supported in target 'xc9500xl'.
(Of course, the info between the ' ' varies according to the device)
I haven't completed a thorough check, but it seems these errors are related to those devices I edited ("copy of...."). I also noticed in my source list there is a list of instantiations for all of the symbols/modules I edited/created (I also did build a few schematics to create single symbols for a collection of multiple devices...a submodule, I guess). In this instantiation list, each of my 'copy of...' modules has a kind of "new file symbol" (dog-eared page?) with a "?" inside at the beginning of each device name in the list. I assume this means the symbol cannot be recognized. For my main design and the major submodules I added as a source, the dog-eared page icon has a (and) gate inside of it.
It certainly appears that editing the symbol isn't working as straightforward as I believe it should. Anyone provide me with some insight how to fix this?