UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
8,229 Views
Registered: ‎12-06-2008

Editor question/issue

Jump to solution

I am new to fpga stuff, this is a fairly basic question. I am using the iSE10.1 webpack with the Avent $39 spartan eval board.

 

I can understand, follow, and create the "blinking led" in the iSE10.1 quick start guide, which is nearly identical to the Avent spartan eval board docs with success, it runs, and blinks the LED as I expect. I can also trivially modify that file in various ways.  :-)

 

I then try to create a new more complex project, in this case - a micro interface module, which has  the normal 'memory type interface signals' (cs, rd, wr, address, data).

 

I use the createa new module, "verilog" and define the In/Outsignals. Eventually, I am done and I get to the "summary screen" and finish the process.

 

In the sources (implimentation) window, I have 2 items;

    "foobar" and "xc3s400a-4ft256"

Functionally identical to the screen shot in the ISE Quick Start Guide.

 

Under the Xilinx tutorial, you create the 1st module - while creating the project (ie: create the first module as you are creating the project)

 

Under the Avent tutorial, they suggest you skip that step, and add it later (ie: create the project, *THEN* create the 1st module)

 

In the end, I have 2 tabs visible, "foo.v" and "Design Summary"

 

I then start editing the "foo.v" file - adding comments, and typing various things in. 

 

Eventually I *SAVE* the "foo.v" file because I want to "check the syntax".

 

 

Per the tutorial screen shots - the file "foo.v" should be *UNDER* the chip - not under the project name.

An example of what I mean is shown on page 14 of "ISE Quick Start Tutorial" 9 figure 6, "New Project in ISE"

 

Sometimes - not always (80% of the time) some how the "foo.v" file moves to under the project name.

 

Questions:

 

(A) what is the proper names for these locations?

(B) what the difference between the two locations?

(C) How do I move the file *back* to under the chip?

 

Why? Because, if it is under the "project name" - I cannot for example check the syntax, and none of the process things work.

 

I'm sort of stuck.

 

-Duane.

 

 

 

 


 

 

 

0 Kudos
1 Solution

Accepted Solutions
Instructor
Instructor
9,948 Views
Registered: ‎08-14-2007

Re: Editor question/issue

Jump to solution

Sorry, too quick on the "post" button.

 

Here goes:

 

Questions:

 

(A) what is the proper names for these locations?

I'm not sure, but the upper area usually contains documents that are not part of your build hierarchy

which could include header files or anything you want to double-click and edit from the ISE Navigator.

When a Verilog source ends up here, it means the file syntax has caused the automatic hierarchy

builder to think this is no longer a module.  Examples of things that can cause this are `ifdef without

a matching `endif, or another syntax error which may cause the endmodule line to be ignored.

 

The area below the chip is where all buildable sources should show.

 

(B) what the difference between the two locations?

upper location - good for documents, bad place for source files.

lower location - good for sources.

 

(C) How do I move the file *back* to under the chip?

fix the syntax errors.

 

Why? Because, if it is under the "project name" - I cannot for example check the syntax, and none of the process things work.

 

Oh? You want the syntax checker to check syntax when you need to find the error?  What a

delightfully innovative approach :-)  Maybe Xilinx should have thought of it...

 

I'm sort of stuck.

 

-Duane.

 

It's a bit of a pain, but you could use the command line interface to try to compile the file that

won't go into the proper hierarchy location so you can get the error messages.  Maybe one of

the command line guru's can help on that.  There are many people who completely throw

out the ISE project navigator and do all their project management with perl scripts batch

files or tcl scripts instead.  Theoretically the GUI whould make life easier, but you've

found a case where the automatic "sensing" of the file type can be a headache.

 

Also if you have access to ModelSim you could use that to check the file syntax.

 

Good luck,

Gabor

Message Edited by gszakacs on 12-06-2008 06:07 PM
-- Gabor
0 Kudos
3 Replies
Instructor
Instructor
9,949 Views
Registered: ‎08-14-2007

Re: Editor question/issue

Jump to solution

Sorry, too quick on the "post" button.

 

Here goes:

 

Questions:

 

(A) what is the proper names for these locations?

I'm not sure, but the upper area usually contains documents that are not part of your build hierarchy

which could include header files or anything you want to double-click and edit from the ISE Navigator.

When a Verilog source ends up here, it means the file syntax has caused the automatic hierarchy

builder to think this is no longer a module.  Examples of things that can cause this are `ifdef without

a matching `endif, or another syntax error which may cause the endmodule line to be ignored.

 

The area below the chip is where all buildable sources should show.

 

(B) what the difference between the two locations?

upper location - good for documents, bad place for source files.

lower location - good for sources.

 

(C) How do I move the file *back* to under the chip?

fix the syntax errors.

 

Why? Because, if it is under the "project name" - I cannot for example check the syntax, and none of the process things work.

 

Oh? You want the syntax checker to check syntax when you need to find the error?  What a

delightfully innovative approach :-)  Maybe Xilinx should have thought of it...

 

I'm sort of stuck.

 

-Duane.

 

It's a bit of a pain, but you could use the command line interface to try to compile the file that

won't go into the proper hierarchy location so you can get the error messages.  Maybe one of

the command line guru's can help on that.  There are many people who completely throw

out the ISE project navigator and do all their project management with perl scripts batch

files or tcl scripts instead.  Theoretically the GUI whould make life easier, but you've

found a case where the automatic "sensing" of the file type can be a headache.

 

Also if you have access to ModelSim you could use that to check the file syntax.

 

Good luck,

Gabor

Message Edited by gszakacs on 12-06-2008 06:07 PM
-- Gabor
0 Kudos
Historian
Historian
8,194 Views
Registered: ‎02-25-2008

Re: Editor question/issue

Jump to solution

Never keep your source files in the same directory as the Xilinx tools "project stuff" (like the ISE file, etc).

 

Create a directory tree like:

 

myprj\src     <- keep sources here

myprj\fit     <- ISE stuff goes here

myprj\tb      <- testbench goes here

 

First create the project in the fit directory. DO NOT ADD ANY SOURCES yet.

 

Now always create your source files OUTSIDE of ISE (don't even use the ISE editor, use emacs instead). Then ADD them to the project (from the "Project" menu). (At last, Xilinx figured out that when you do "add source to project" it SHOULD NOT copy the source to the fitter project directory.)

 

After adding sources,  make sure the sources are visible ("View Sources" has a checkmark) then make sure that window shows Sources For and "Implementation" is selected. You should see a tree with the FPGA device at the top, and all of the sources in the hierarchy below it.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
8,173 Views
Registered: ‎12-06-2008

Re: Editor question/issue

Jump to solution

Thanks to both of you - for your help.

 

And yes emacs now comes with Verilog mode :-) ... much easier that way!

 

0 Kudos