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Explorer
Explorer
6,522 Views
Registered: ‎02-10-2016

Elaboration issue

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Hi,

 

I am driving 2 output ports, SFP0_TX_p and SFP0_TX_n by ground (see attached BD). When I elaborate them, they dissapear from elaboration schematic and their status looks strange (see attached elaboration). I need to attach them, to external FPGA pins and constraints fail to find them.

What can I do?

 

TIA,

Nikos

BD.png
Elaboration.png
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1 Solution

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Xilinx Employee
Xilinx Employee
12,417 Views
Registered: ‎07-31-2012

Re: Elaboration issue

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hi nikos, You can try using the KEEP or DONT_TOUCH attribute which helps save nets and hence possibly ports. Please check - Pg 39, 41 of this guide for help - http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug901-vivado-synthesis.pdf
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
7 Replies
Xilinx Employee
Xilinx Employee
6,489 Views
Registered: ‎07-31-2012

Re: Elaboration issue

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From the schematics it does seem the ports exists.

However why are you giving the ports in the 1st place when you want to ground them?
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Explorer
Explorer
6,486 Views
Registered: ‎02-10-2016

Re: Elaboration issue

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Hi @Anirudh,

 

As mentioned, ports exist in BD, because I placed them there. They don't show in elaboration schematic, or in TCL with get_ports. If I list all ports and search for them, they will show up in a weird state. My question is:

 

What does that state mean? How can I recover it?

 

The reason I need these external ports, is that FPGA has already an external pin layout, and rest of board hardware counts on it being there.

 

PS: Putting an OBUF in the path before them, doesn't affect their state.

 

BR,

Nikos

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Xilinx Employee
Xilinx Employee
12,418 Views
Registered: ‎07-31-2012

Re: Elaboration issue

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hi nikos, You can try using the KEEP or DONT_TOUCH attribute which helps save nets and hence possibly ports. Please check - Pg 39, 41 of this guide for help - http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug901-vivado-synthesis.pdf
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
Explorer
Explorer
6,472 Views
Registered: ‎02-10-2016

Re: Elaboration issue

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Hi @Anirudh,

 

Thanks for your efforts, but I don't see a way to place attributes in BD, only in verilog. Besides, connected net is ground, not a nice place to use KEEP or DON'T TOUCH :(

 

This state must be a standard vivado state. What does it mean and how can I fix it?

 

BR,

Nikos

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Xilinx Employee
Xilinx Employee
6,469 Views
Registered: ‎07-31-2012

Re: Elaboration issue

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Not sure how successfully this would work, but I would recommend bring the bd port to a top wrapper file and then assign a net to it and try applying the KEEP attribute. You can assign that net to an ouput port in the wrapper.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
Explorer
Explorer
6,465 Views
Registered: ‎02-10-2016

Re: Elaboration issue

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Hi @Anirudh,

 

I think I better wait for smt more straightforward. This doesn't sound very promising, and a lot could go wrong. I'm not sure I'm up to the level.

 

BR,

Nikos

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Explorer
Explorer
6,410 Views
Registered: ‎02-10-2016

Re: Elaboration issue

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Deleted my last post, since it was the wrong approach. My issue turns out to be completely different, so I'll be closing this thread.

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