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Adventurer
Adventurer
951 Views
Registered: ‎02-08-2016

Elaboration problem due to trying to add verilog files to existing system verilog design unit

Hi,

 

I use Vivado to build our ASIC RTL for design emulation / verification purposes.

 

Typically our designs are 500-1000 files of SystemVerilog and some verilog files

Time and again my time is wasted by the following problem.

 

for example :

 

I read the 500 SystemVerilog design rtl files into vivado . This is analysed by teh Vivado tools and a SystemVerilog design unit is created.

 

I attempt elaboration/synthesis to explore/debug the design and find I need to add further files

e.g. one of the .sv files has an 'include "abc.v" statement

 

I go and find the missing abc.v file and I read it into Vivado. I can see the file in the source list

 

I attempt elaboration and elaboration fails. The error message still says the file is missing

 

---

 

The reason for the above is that a design unit for systemverilog has been created , but the new file abc.v cannot be compiled into this design unit. so the design can never be compiled. How do I destroy the initial design unit and get vivado to re-read all the files again into one unit?

 

Regards Simon

 

 

 

 

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Moderator
Moderator
941 Views
Registered: ‎09-15-2016

Hi @simonh_bwt

 

Can you open the .xpr file  present in the project directory in the text editor and search for abc.v file. If there is a definition of abc.v file there, then remove it and save the .xpr file. Now again open the project and add the file again. 

Let us know if it helps.

 

Regards

Rohit

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Regards
Rohit
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