06-27-2018 05:18 PM - edited 06-27-2018 05:32 PM
I have done some digging on this topic on the internet, and it seems to quite a few say it's not possible to encrypt netlist .edn file because it doesn't comply with IEEE standard. Is it still the case in 2018?
Below are the two approaches we have tried so far,
1. Encrypt all RTL source files using `encrypt -key key_file -lang verilog -ext .svp ` first, run synthesis, and `write_edif -security_mode all ` to get a single specified encrypted EDIF file.
2. Synthesise the design and get the unencrypted netlist .v file first, encrypt it using `encrypt -key key_file -lang verilog -ext .svp `, import it back into Vivado, and run `write_edif -security_mode all ` to get a single specified encrypted EDIF file.
It seems that neither works as Vivado complains: `ERROR: [Designutils 20-2284] Design protected by IEEE 1735 V2 may not be written to EDIF.`
06-27-2018 06:07 PM
It is not possible to use write_edif for writing netlist on the encrypted files. You can use write_verilog or write_vhdl to write the netlist for the design with encrypted sources. Ideally the netlist generated from the above commands would have the encrypted source of design elements.
07-05-2018 03:02 AM - edited 07-05-2018 03:07 AM
According to Xilinx Tcl command reference guide, write_edif can actually output encrypted edif file, on the premises that the following lines of code are added after module declaration of the .v netlist file.
(* secure_config = "protect" *)
(* secure_netlist = "encrypt" *)
(* secure_net_editing = "prohibit" *)
(* secure_net_probing = "prohibit" *)
Execute wirte_edif and it should give you an encrypted edn file.
I think this is Xilinx's proprietary way to do edif encryption, and this is not compatible to IEEE standard.