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Adventurer
Adventurer
642 Views
Registered: ‎08-07-2018

Error declaring signal of type vec_16x16 in VHDL simulation file.

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Greetings ... a couple of days ago I have been doing the simulation of certain modules of a project independently in Vivado 2017.3, I have managed to perform the simulation of some of these modules but I have problems with one (g1_lbus.vhd) when creating the file of simulation since it gives me the following error that is shown in the attached image this or not this declared signal i_cpu_rd_dat: vec_16x16 in the simulation file (g1_lbus_tb.vhd).

LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.std_logic_unsigned.all;
  USE ieee.std_logic_misc.all;
  USE ieee.numeric_std.all;
  --USE work.g1_common_pkg.all;
LIBRARY unisim;
  USE unisim.vcomponents.all;

entity g1_lbus_tb is
--  Port ( );
end g1_lbus_tb;

architecture Behavioral of g1_lbus_tb is

Component g1_lbus
    port(
        --External local bus interface to/from G3
       i_reset            : in    std_logic;     --Async reset   
       i_lclk             : in    std_logic;     --Local bus clock
       i_lbus_cs_l        : in    std_logic;
       i_lbus_rnw         : in    std_logic;
       i_lbus_addr        : in    std_logic_vector(19 downto 0);
       o_lbus_lgta_l      : out   std_logic;   
       io_lbus_data       : inout std_logic_vector(15 downto 8);
       io_smap_lbus_data  : inout std_logic_vector(7 downto 0);
       
       --Internal local bus interface to/from FPGA fabric
       o_blk_sel          : out   std_logic_vector(15 downto 0);
       o_cpu_rnw          : out   std_logic;
       o_cpu_addr         : out   std_logic_vector(19 downto 0); 
       o_cpu_wr_dat       : out   std_logic_vector(15 downto 0);
       i_cpu_ta           : in    std_logic_vector(15 downto 0)
       i_cpu_rd_dat       : in    vec_16x16
    );
    end component;
   --External local bus interface to/from G3
   signal i_reset            :     std_logic;     --Async reset   
   signal i_lclk             :     std_logic;     --Local bus clock
   signal i_lbus_cs_l        :     std_logic;
   signal i_lbus_rnw         :     std_logic;
   signal i_lbus_addr        :     std_logic_vector(19 downto 0);
   signal o_lbus_lgta_l      :    std_logic;   
   signal io_lbus_data       :  std_logic_vector(15 downto 8);
   signal io_smap_lbus_data  :  std_logic_vector(7 downto 0);
   
   --Internal local bus interface to/from FPGA fabric
   signal o_blk_sel          :    std_logic_vector(15 downto 0);
   signal o_cpu_rnw          :    std_logic;
   signal o_cpu_addr         :    std_logic_vector(19 downto 0); 
   signal o_cpu_wr_dat       :    std_logic_vector(15 downto 0);
   signal i_cpu_ta           :     std_logic_vector(15 downto 0);
   signal i_cpu_rd_dat       :     vec_16x16; 
   constant clk_100MHz : time := 10 ns;-- for 100 MHz    
begin

UUT: g1_lbus
port map(

    i_reset            =>     i_reset,       
    i_lclk             =>     i_lclk,     
    i_lbus_cs_l        =>     i_lbus_cs_l,
    i_lbus_rnw         =>     i_lbus_rnw,
    i_lbus_addr        =>     i_lbus_addr,
    o_lbus_lgta_l      =>     o_lbus_lgta_l,   
    io_lbus_data       =>    io_lbus_data,
    io_smap_lbus_data  =>    io_smap_lbus_data,

    o_blk_sel          =>    o_blk_sel,
    o_cpu_rnw          =>    o_cpu_rnw,
    o_cpu_addr         =>    o_cpu_addr, 
    o_cpu_wr_dat       =>    o_cpu_wr_dat,
    i_cpu_ta           =>    i_cpu_ta
    i_cpu_rd_dat       =>     i_cpu_rd_dat  
);

Clk100MHz :process
  begin
        i_lclk <= '0';
        wait for clk_100MHz/2;  --for half of clock period clk stays at '0'.
        i_lclk <= '1';
        wait for clk_100MHz/2;  --for next half of clock period clk stays at '1'.
  end process;
end Behavioral;

Could someone please tell me why this error is due. Thanks in advance.
I leave the file g1_lbus.vhd attached

errorVivado.PNG
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1 Solution

Accepted Solutions
626 Views
Registered: ‎06-21-2017

Re: Error declaring signal of type vec_16x16 in VHDL simulation file.

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Is VEC16x16 a declared type in a package file somewhere?  You did not include a library indicating that it is.  You need to declare an array.

 

TYPE VEC16x16 is array (0 to 15) of std_logic_vector(15 downto 0);

 

Include this in a package file or put this declaration before you use it to declare your signals and components.

4 Replies
627 Views
Registered: ‎06-21-2017

Re: Error declaring signal of type vec_16x16 in VHDL simulation file.

Jump to solution

Is VEC16x16 a declared type in a package file somewhere?  You did not include a library indicating that it is.  You need to declare an array.

 

TYPE VEC16x16 is array (0 to 15) of std_logic_vector(15 downto 0);

 

Include this in a package file or put this declaration before you use it to declare your signals and components.

Adventurer
Adventurer
607 Views
Registered: ‎08-07-2018

Re: Error declaring signal of type vec_16x16 in VHDL simulation file.

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Thanks for answering @bruce_karaffa, looking for the project I found a statement of this type in the following file g1_common_pkg.vhd.

LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.std_logic_unsigned.all;
  USE ieee.std_logic_misc.all;
  USE ieee.numeric_std.all; 


---------------------------------------------------

package g1_common_pkg is

  
  --General array's that are defined for use in different sections of the design     
  type vec_2x2   is array(0 to 1)  of std_logic_vector(  1 downto 0);
  type vec_2x4   is array(0 to 1)  of std_logic_vector(  3 downto 0);
  type vec_2x16  is array(0 to 1)  of std_logic_vector( 15 downto 0);
  type vec_3x4   is array(0 to 2)  of std_logic_vector(  3 downto 0);
  type vec_3x16  is array(0 to 2)  of std_logic_vector( 15 downto 0);
  type vec_3x100 is array(0 to 2)  of std_logic_vector( 99 downto 0);
  type vec_4x2   is array(0 to 3)  of std_logic_vector(  1 downto 0);
  type vec_4x4   is array(0 to 3)  of std_logic_vector(  3 downto 0);
  type vec_4x8   is array(0 to 3)  of std_logic_vector(  7 downto 0);
  type vec_4x16  is array(0 to 3)  of std_logic_vector( 15 downto 0);
  type vec_4x32  is array(0 to 3)  of std_logic_vector( 31 downto 0);
  type vec_4x18  is array(0 to 3)  of std_logic_vector( 17 downto 0);
  type vec_4x20  is array(0 to 3)  of std_logic_vector( 19 downto 0);
  type vec_4x256 is array(0 to 3)  of std_logic_vector(255 downto 0);
  type vec_8x4   is array(0 to 7)  of std_logic_vector(  3 downto 0);
  type vec_8x8   is array(0 to 7)  of std_logic_vector(  7 downto 0);
  type vec_8x16  is array(0 to 7)  of std_logic_vector( 15 downto 0);
  type vec_8x20  is array(0 to 7)  of std_logic_vector( 19 downto 0);
  type vec_8x32  is array(0 to 7)  of std_logic_vector( 31 downto 0);
  type vec_8x64  is array(0 to 7)  of std_logic_vector( 63 downto 0);
  type vec_12x16 is array(0 to 11) of std_logic_vector( 15 downto 0);
  type vec_16x16 is array(0 to 15) of std_logic_vector( 15 downto 0);
  type vec_18x8  is array(0 to 17) of std_logic_vector(  7 downto 0);
  type vec_19x8  is array(0 to 18) of std_logic_vector(  7 downto 0);
  type vec_18x16 is array(0 to 17) of std_logic_vector( 15 downto 0);
  type vec_19x16 is array(0 to 18) of std_logic_vector( 15 downto 0);
  type vec_32x16 is array(0 to 31) of std_logic_vector( 15 downto 0);
  type vec_32x20 is array(0 to 31) of std_logic_vector( 19 downto 0);

  type vec_2x32b  is array(0 to 2)  of std_logic_vector(0 to  31);
  type vec_2x256b is array(0 to 2)  of std_logic_vector(0 to 255);
  type vec_4x32b  is array(0 to 3)  of std_logic_vector(0 to  31);
  type vec_4x256b is array(0 to 3)  of std_logic_vector(0 to 255);
  
  constant s1    : integer := 1;
  constant s0    : integer := 0;

end package g1_common_pkg;

Then should I add a library USE work.g1_common_pkg.all to my simulation file?

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604 Views
Registered: ‎06-21-2017

Re: Error declaring signal of type vec_16x16 in VHDL simulation file.

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Yes. that should fix the problem

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Adventurer
Adventurer
595 Views
Registered: ‎08-07-2018

Re: Error declaring signal of type vec_16x16 in VHDL simulation file.

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Yes, in part, although it was necessary to add the document g1_common_pkg.vhd in the libraries tab of the project. Then I closed Vivado and returned to open the project again and that way it worked for me.

addLibrary.PNG
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