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Adventurer
Adventurer
12,561 Views
Registered: ‎03-30-2012

FIFO Generator 9.2 "synth" file causes problems in synthesis?

Hi:

 

Using FIFO Generator 9.2, when the IP is regenerated, it creates the following two files (for a FIFO named fifoname)

 

fifoname.v

fifoname_synth.v

 

These two files get added to the project's compile list in the XCO (not sure how - I think the fifoname_xmdf.tcl does it). The problem is, they're *both* added to the compile list, and they *both* define a module named "fifoname."

 

So when I try to synthesize the project, I get...

 

Analyzing Verilog file "C:\cygwin\home\barawn\repositories\ISE_test\par\ipcore_dir\fifoname.v" into library work
Parsing module <fifoname>.
Analyzing Verilog file "C:\cygwin\home\barawn\repositories\ISE_test\par\ipcore_dir\fifoname_synth.v" into library work
Parsing module <fifoname>.
ERROR:HDLCompiler:687 - "C:\cygwin\home\barawn\repositories\ISE_test\par\ipcore_dir\fifoname_synth.v" Line 54: Illegal redeclaration of module <fifoname>.
Verilog file C:\cygwin\home\barawn\repositories\ISE_test\par\ipcore_dir\fifoname_synth.v ignored due to errors

 

If you manually remove "fifoname_synth.v", it compiles and simulates fine (if you remove fifoname.v, it synthesizes fine but doesn't simulate because fifoname_synth is an empty module).

 

Is there some way to fix this problem (or has anyone else seen it)? I have a feeling that fifoname_synth.v is supposed to be for implementation only, and fifoname.v is supposed to be for simulation only, but it doesn't seem to be working like that. I don't think I'm doing anything weird so I'm a bit surprised I haven't seen this problem mentioned anywhere.

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9 Replies
Xilinx Employee
Xilinx Employee
12,555 Views
Registered: ‎07-22-2008

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?

There are two places where the files of an IP core subproject (.xco file) are specified to be added to a specific view (e.g. simulation of implementaion).

The first is the <core_name>_xmdf.tcl file as you've discovered.

The second is the <core_name>.xise file.

You could work around this problem by:

   1) Opening the <core_name>.xise file as a project in Project Navigator and changing the view of the file(s) in question to the desired view only

   2) Editing the xmdf file and comment out of change files to type ignore

   3) Delete the core from the original project and add it back again.

 

This issue has been reported to Xilinx IP developemnt.

When available, a more comprehensive solution will be made available at: http://www.xilinx.com/support/answers/51200.htm.

 

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Xilinx Employee
Xilinx Employee
12,552 Views
Registered: ‎07-22-2008

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?

 From the reports I've seen, the _snth file is created irroneously.  Synthesis could proceed if the _synth file was just removed from the IP_cores directory.  Note that there would be a warning stating that the file could not be found.

 

Alternatively, the issue may be resolved by doing the following

 1 - Removing fifo core from ISE project

 2 - Editing the <fifo_core_name>_xmdf.tcl file and commenting out the following lines

For VHDL flow:

 utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path <fifo_core_name>_synth.vhd

 utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl

 incr fcount

For Verilog flow:

utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path <fifo_core_name>_synth.v

utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog

incr fcount

 3 - Adding the fifo core back into the project.

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Contributor
Contributor
12,543 Views
Registered: ‎05-19-2010

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?

This is also causing problems for simulation - the outputs of FIFOs are undefined (FIFO replaced by empty definition).

In the compilation window I see:

 

Parsing VHDL file "/home/daniel/work/OFZ_TX/ipcore_dir/FIFO_9to9_1k.vhd" into library work
Parsing VHDL file "/home/daniel/work/OFZ_TX/ipcore_dir/FIFO_9to9_1k_synth.vhd" into library work
WARNING:HDLCompiler:685 - "/home/daniel/work/OFZ_TX/ipcore_dir/FIFO_9to9_1k_synth.vhd" Line 57: Overwriting existing primary unit fifo_9to9_1k

 

Deleting the FIFO..._synth.vhd file fixes the problem.

 

Daniel

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Observer retni
Observer
12,412 Views
Registered: ‎11-26-2010

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?

seems we met the same problem, and i have post it also:

http://forums.xilinx.com/t5/Design-Entry/ISE14-2-when-i-instantiate-the-fifo-ipcore-with-xco-file-there/td-p/259770

 my solution is to remove the .xco file, and add the .v file and the .ngc file to the project, and it can be simulated and implemented.

Moderator
Moderator
12,272 Views
Registered: ‎11-04-2010

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?

This issue is fixed in fifo_generator_v9_3 version.

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Newbie asin
Newbie
12,081 Views
Registered: ‎11-01-2012

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?

i met the same error. 

 

i want to know how to update 9.2 to 9.3? i'm a freshman on ISE.

 

thanks very much! 

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Historian
Historian
12,063 Views
Registered: ‎02-25-2008

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?


@asin wrote:
i want to know how to update 9.2 to 9.3? i'm a freshman on ISE.

Uhhh, download and install it?

----------------------------Yes, I do this for a living.
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Newbie dlitz
Newbie
11,957 Views
Registered: ‎11-18-2012

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?


asin wrote:

i want to know how to update 9.2 to 9.3? i'm a freshman on ISE.


According to this, you need to upgrade to ISE 14.3 / Vivado 2012.3 in order to get it.  Upgrading from ISE WebPACK from 14.2 to 14.3 worked for me.

 

Good luck!

0 Kudos
7,951 Views
Registered: ‎06-04-2013

Re: FIFO Generator 9.2 "synth" file causes problems in synthesis?

Hello,

 

I have come to this page looking for a solution to "Illegal redeclaration of module

 

All the methods, though didn't solve my issue, helped me in resolving the issue.

 

In my case, I made a copy of a project into a different folder and started developing on the new copy. Now the ise is looking the core .v file in old path and new path. It is using absolute paths so, it finds files in both the paths and thus the error.

 

Fix: Just renaming the old folder worked. There could be more elegant solution that I will look for now.

 

Posting it so that someone who falls in my case could get benifited.

 

Cheers,

Praveen.

http://praveenkumar.co.in

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