03-05-2010 05:04 PM
I am trying to implement a FIR filter on a Spartan 3E dev board. I am using PMOD's for the ADC and DAC (both 12bit) and have working code for them. So, next step is implement a FIR filter. So far, I have tried this with both CORE Generator and System Generator. Once I generate a bit file, the program just passes whatever comes in the ADC to the DAC (i.e. no signal degradation or anything - just straight through).
I've simulated this with simulink and can get a FIR filter to work. But, simulation and reality are two different things, I understand.
On a side note, since the data coming in the ADC is between 0-3.3VDC, that corresponds to 0-4095 (12bit) in the program. And, the data going to the DAC is the same. I'm wondering if using 12bit unsigned data along with the filter coefficients is causing a problem. I changed just about every option for the filter coefficients and no luck. I also tried a basic averaging filter and get the same "straight through" response.
Does anyone have any clues/pointers for me? I am somewhat new to this. Any advice is GREATLY appreciated.
03-09-2010 04:57 AM - edited 03-09-2010 04:57 AM
03-12-2010 12:07 PM
As a newbie, I apologize if I say anything contradictory or just plain stupid. Please attribute that to my ignorance.
For system generator, I understand that anything coming in is fixed point; one just sets the bit width and binary point. I'm using the DDS Compiler to generate a sign wave, which the output is set to 8 bits and binary point set to 7. For the FIR Compiler, I have the the coefficient bit width set to 8 and binary point set to 7. As for the coefficients, I've imported them via fdatool, manually typed them in, and used the fir1 and firpm commands (same cutoff, order #, etc, values for all three methods). I simulate this setup and change the output frequency of the DDS Compiler. Every time I do this, the filter output amplitude is lower in amplitude than the incoming signal; however, the filter output amplitude never changes based on the incoming frequency. However, in simulink (i.e. non-xilinx blocksets) this setup works. It also works in Matlab via command line.
I have not used Modelsim for this design, nor have I ever used Modelsim. I'll look into that; I know I have it.
As for the kind of hw synthesized in order to support my design ... ummm ... not sure if I understand exactly what you're asking, but I have a spartan 3e dev board and I'm generating verilog code. I couldn't infer what you might be asking from viewing the synthesis report either. Again, I apologize for my ignorance.