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Visitor
Visitor
1,063 Views
Registered: ‎02-26-2019

FREQ_HZ and Clock domain crossing

Hello,

I am using a Tri Mode Ethernet MAC along with a AXI direct memory access in my design.

When I have my design ready, the Synthesis fails due to the errors listed below:

  • [BD 41-237] Bus Interface property FREQ_HZ does not match between /tri_mode_ethernet_mac_0/s_axis_tx(125000000) and /axi_dma_0/M_AXIS_MM2S(100000000)
  • [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /tri_mode_ethernet_mac_0/s_axis_tx(/clk_wiz_clk_out1) and /axi_dma_0/M_AXIS_MM2S(design_1_processing_system7_0_0_FCLK_CLK0

The properties are locked and read only, the result is not reflected after changing the xml and xci constraints. Also Clock converter and AXI Interconnect are not effective 

Awaiting your suggestions

Thank you

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4 Replies
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Moderator
Moderator
1,039 Views
Registered: ‎03-16-2017

Hi @ssh24 ,

 

Have a look, these looks similar: 

https://forums.xilinx.com/t5/Welcome-Join/BD-41-237-Bus-Interface-property-FREQ-HZ-does-not-match/td-p/775283

https://www.xilinx.com/support/answers/56611.html

 

Regards,
hemangd

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Visitor
Visitor
1,018 Views
Registered: ‎02-26-2019

Hello @hemangd,
Thank you for the suggestions.

But unfortunately that doesn't seem to work as well. The Slave does not connects itself to the external port and also error persists after removing the FREQ_HZ Parameters.
Please help.

Regards,
ssh24
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Moderator
Moderator
979 Views
Registered: ‎11-09-2015

HI @ssh24 ,

You need to connect both interfaces to the same clock (clk_wiz_clk_out1) or you need to use an AXI interconnect to do clock domain crossing


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Community Manager
Community Manager
930 Views
Registered: ‎05-08-2017

Hi @ssh24 ,

If your issue is solved, please mark an appropriate response as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions), so the topic can be completed then. We appreciate your help.

Thanks in advance and have a great day.
Kind Regards,
Devin Lance,
Xilinx Technical Support

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