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m5231124
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Registered: ‎09-10-2019

Fail to create clock wizard Vivado 2019.2

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Hello. I am a very beginner in Vivado, and tried to create a quite simple project to control LEDs for Ultra96v2 with Clocking Wizard and some other IPs. But I got an error as followed when I tried to create a Clocking Wizard.

 

startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
ERROR: [Common 17-49] Internal Data Exception: File is XNG_UNKNOWN format '/opt/Xilinx/Vivado/2019.2/data/./parts/xilinx/zynquplus/devint/zynquplus/xczu3eg/xczu3eg.xng'
ERROR: [IP_Flow 19-3476] Tcl error in create_gui procedure for BD Cell 'design_1_clk_wiz_0_0'.
ERROR: [IP_Flow 19-3428] Failed to create Customization object design_1_clk_wiz_0_0
CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'design_1_clk_wiz_0_0'. Failed to customize IP instance 'design_1_clk_wiz_0_0'. Failed to load customization data
ERROR: [BD 41-1712] Create IP failed with errors
ERROR: [BD 5-7] Error: running create_bd_cell -vlnv xilinx.com:ip:clk_wiz:6.0 -type ip -name clk_wiz_0 .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
endgroup

 

I looked through other report about Clocking Wizard [https://forums.xilinx.com/t5/Timing-Analysis/Vivado-2018-3-Clocking-Wizard-is-broken/td-p/922966]

and changed the system language setting to English US, but it did not work.

 

Actually, with other FPGA target board design Clocking Wizard was successfully created.

 

Could anyone help me? Thank you.

 

OS: Ubuntu 16.04 LTS

Vivado 2019.2

Target Board Ultra96v2

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ashishd
Xilinx Employee
Xilinx Employee
710 Views
Registered: ‎02-14-2014

Hi @m5231124 ,

There seems a link between md5sum mismatch and errors which you are observing as the errors are related to files in installation repository. It would be worth to sort out problems related to 'Download Verification' aspect first, before actually moving on to installing the software. This 'Download Verification' step is completely optional but highly recommended in order to ensure authenticity and integrity of the software. It would also be worth giving a try with standalone Vivado Design Suite installation (Initially I have tried reproducing problem with standalone Vivado itself). It will help in debugging the problem further.

Regards,
Ashish
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6 Replies
ashishd
Xilinx Employee
Xilinx Employee
796 Views
Registered: ‎02-14-2014

Hi @m5231124 ,

I tried reproducing this problem using em.avnet.com:ultra96:part0:1.2 board (you can cross check if this matches with yours using command get_property board_part [current_project] ). But for me, clocking wizard is correctly getting added to block design. Here is the log -

create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
create_bd_cell: Time (s): cpu = 00:00:33 ; elapsed = 00:01:03 . Memory (MB): peak = 7903.891 ; gain = 906.750 ; free physical = 24916 ; free virtual = 31174
/clk_wiz_0 

INFO message is correct as there are no PL interfaces defined for Ultra96 board as per board files. So the sole purpose of board files is to configure MPSoC with predefined preset and then generate necessary output products (and eventually bitstream). This is the OS I used -

Distributor ID: Ubuntu
Description: Ubuntu 16.04.1 LTS
Release: 16.04

Few pointers in order to debug this further -

1. Are you able to add any other board aware IP to block design without any issue ? Try adding axi_gpio, axi_uartlite etc.

2. Are you able to add clocking wizard to project outside block design? In other words, is below command successful ? -

create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_0

3. Is this problem consistent across different machines ?

Regards,
Ashish
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m5231124
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Registered: ‎09-10-2019

Hello @ashishd. Thank you for your quick and kind reply!

 

I found one critical mistake when I tried changing a machine as you suggested, and fixed it. But still can not create a Clocking Wizard ip for Ultra96v2.

 

Actually, when I first installed Vivado 2019.2, installation failed somehow on the way half so I reinstalled it in other place in local but not DocNav and Model_Composer because they two seemed to be installed successfully. But I noticed setting64.sh files for them referred an old crushed (or failed)  Vivado place, so I reinstalled Vivado 2019.2 again.

 

And then, still can not create a Clocking Wizard ip, but error messages changed.

 

startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
ERROR: [Common 17-49] Internal Data Exception: Could not parse spl file '/opt2/Xilinx/Vivado/2019.2/data/parts/xilinx/zynquplus/devint/zynquplus/xczu3eg/xczu3eg.paspd'
ERROR: [IP_Flow 19-3188] Error occurred while initializing 'design_1_clk_wiz_0_0'
Tcl error in validate procedure while setting value '100.000' on parameter 'CLKOUT1_REQUESTED_OUT_FREQ'. .

ERROR: [IP_Flow 19-3428] Failed to create Customization object design_1_clk_wiz_0_0
CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'design_1_clk_wiz_0_0'. Failed to customize IP instance 'design_1_clk_wiz_0_0'. Failed to load customization data
ERROR: [BD 41-1712] Create IP failed with errors
ERROR: [BD 5-7] Error: running create_bd_cell -vlnv xilinx.com:ip:clk_wiz:6.0 -type ip -name clk_wiz_0 .
create_bd_cell: Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 7617.645 ; gain = 786.055 ; free physical = 9891 ; free virtual = 13760
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
endgroup

 

These errors seemed to be same with [https://forums.xilinx.com/t5/Installation-and-Licensing/ERROR-Common-17-49-Internal-Data-Exception-Could-not-parse-spl/td-p/403367] and it says to check if installed files are correct, but I have no idea how I can check it on Ubuntu16.04 because the solution recommends to use a software which only works on Windows machines.

 

Could you help me again? Thank you for your kind help.

 

 

Just in case, I wrote down the results of pointers you suggested for a debug.

 

1. Are you able to add any other board aware IP to block design without any issue ? Try adding axi_gpio, axi_uartlite etc.

Yes. Both two ips were successfully created.

 

2. Are you able to add clocking wizard to project outside block design? In other words, is below command successful ? -

create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_0

No. As I type the command on a TCl Console, one popup named "Tcl Command Line" came up and it never finished with a message "Running create_ip...".

 

3. Is this problem consistent across different machines ?

Sorry, I could not try this. I could not prepare any machine with the same environment.

 

P.S. I don't know if this works, but I found an error message on a terminal window running vivado, it says "Error found syntax error, unexpected END, expecting T_Revision at 1.0 Parsing failed ...."

 

Sincerely,

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ashishd
Xilinx Employee
Xilinx Employee
745 Views
Registered: ‎02-14-2014

Hello @m5231124 ,

From your observations, it seems there is some installation corruption w.r.t. zynquplus family devices which is causing this failure. Both files in your former and later error viz. xczu3eg.xng and xczu3eg.paspd are encrypted files in the install repository. You can try few other debugging methods mentioned below which can confirm if this is really the case -

1. Insteading of creating vivado project with Ultra96V2 board, create project with its FPGA part xczu3eg-sbva484-1-e (part based project), and check if you can add clocking wizard to block design.

2. Create new project with any other board from zynquplus family devices. You can use ZCU102, ZCU104, ZCU106 or ZCU111. With this project, try adding clocking wizard to block design.

3. Since download and installation is the suspect, you can check 'Download Verification' section from below UG -

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug973-vivado-release-notes-install-license.pdf#page=33

and this AR for troubleshooting installation related issues - https://www.xilinx.com/support/answers/60118.html

Regards,
Ashish
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m5231124
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Registered: ‎09-10-2019

Hello and Thank you for your kind reply again, @ashishd !

I tried some debugging methods you kindly suggested.

 

1. Insteading of creating vivado project with Ultra96V2 board, create project with its FPGA part xczu3eg-sbva484-1-e (part based project), and check if you can add clocking wizard to block design.

Haven't  tried yet.

2. Create new project with any other board from zynquplus family devices. You can use ZCU102, ZCU104, ZCU106 or ZCU111. With this project, try adding clocking wizard to block design.

Failed to add a Clocking Wizard in both ZCU102 and ZCU104.

3. Since download and installation is the suspect, you can check 'Download Verification' section from below UG -

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug973-vivado-release-notes-install-license.pdf#page=33

and this AR for troubleshooting installation related issues - https://www.xilinx.com/support/answers/60118.html

Tried, and the output of md5sum value does not seem to match with the expected key.

Actually, I installed Vivado2019.2 through "Xilinx Vitis 2019.2: All OS installer Single-File Download  (TAR/GZIP - 30.76 GB)" from [https://japan.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis/2019-2.html] and  tried verifying with a digests file as instructed in "https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug973-vivado-release-notes-install-license.pdf#page=33" (A signature file could not be downloaded with an error message: /tmp/mozilla_s12301640/ysP8h6Jy.sig.part could not be saved, because the source file could not be read. Try again later, or contact the server administrator. ). Although the expected MD5 SUM value is d63bae9cad9bcaa4b2c7f6df9480eaa6, but I got e638f2fd1637a19b9e0ab395e859ebeb.

$ openssl dgst -md5 Xilinx_Vitis_2019.2_1106_2127.tar.gz.digests
MD5(Xilinx_Vitis_2019.2_1106_2127.tar.gz.digests)= e638f2fd1637a19b9e0ab395e859ebeb

 

I could not find any solution when I got mismatched in verifying integrity of installed files, so should I just re-install Vitis files? I don't think I got network or authentication error while installing because a stable wired network was used for installing, and I ran setup command with sudo.

I wonder if installing Vivado through Vitis platform may cause such this failure of creating Clocking Wizard. Should I install Single Vivado Design Suite? (But I would like to use Vitis-AI...)

 

Sorry again for too newbie question. Thank you for your help.

 

Sincerely,

 

 

 

 

 

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ashishd
Xilinx Employee
Xilinx Employee
711 Views
Registered: ‎02-14-2014

Hi @m5231124 ,

There seems a link between md5sum mismatch and errors which you are observing as the errors are related to files in installation repository. It would be worth to sort out problems related to 'Download Verification' aspect first, before actually moving on to installing the software. This 'Download Verification' step is completely optional but highly recommended in order to ensure authenticity and integrity of the software. It would also be worth giving a try with standalone Vivado Design Suite installation (Initially I have tried reproducing problem with standalone Vivado itself). It will help in debugging the problem further.

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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m5231124
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677 Views
Registered: ‎09-10-2019

Heelo @ashishd, I finally solve this problem.

As you suggested, this problem is related to a license for Vivado. It seems I did not set up a license manager correctly when installing Vitis (or just Vivado). It prevented me from creating some provided IPs, and caused some errors on a running terminal as well.

Open license manager, generating license file (Xilinx.lic), then copy it under $HOME/.Xilinx, this led me to successfully put a Clocking Wizard IP.

 

Thank you for your useful replies and tips.

 

Sincerely,

 

 

 

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