12-22-2013 02:18 PM
Is there a way to force an import Out-Of-Context (OOC) module to generate code in verilog, instead of vhdl, in Vivado 2013.4?
12-22-2013 06:24 PM
12-22-2013 09:26 PM
I have set the project settings to verilog, but Vivado 2013.4 generates vhdl code instead of verilog.
e.g. In my IP sources, I have an IP core called cf_ddsx_1. In the synthesis and simulation folders, instead of a verilog file cf_ddsx_1.v, a vhdl file cf_ddsx_1.vhdl is being generated.
Previously with the EDK-14.7, core generator used to generate *.ngc and *.v files.
12-22-2013 09:40 PM
What is the IP core you were using?
Refer to product guide of that IP, to see in what language the output products will be generated.
12-22-2013 09:47 PM
For this specific core as per below PG, I think by default you will get VHDL behavioral models only.
If you need verilog please try write_verilog TCL option on synthesized netlist, this will give you Verilog Structural netlist.
Follow up from below post