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Scholar ronnywebers
Scholar
7,320 Views
Registered: ‎10-10-2014

GMII to RMII - interfacing external ethernet phy (GEM1 through EMIO) - timing failed

Hello,

 

I'm trying to connect GEM1 in the PS to a Marvell Phy on my board. My design currently fails on timing on the rx side (data from the phy to PL). I have attached some screenshots, and the timing report for on of the failing paths in excel format

 

 

in my .xdc file I have added these constraints for the RX side :

 

create_clock -period 8.000 -name RGMII_rxc [get_ports RGMII_rxc]

set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {gmii_clk_25m_out gmii_clk_2_5m_out}] -group [get_clocks -include_generated_clocks gmii_clk_125m_out]

set_input_delay -clock [get_clocks RGMII_rxc] -min 1.200 [get_ports {RGMII_rd[*] RGMII_rx_ctl}]
set_input_delay -clock [get_clocks RGMII_rxc] -max 1.200 [get_ports {RGMII_rd[*] RGMII_rx_ctl}]
set_input_delay -clock [get_clocks RGMII_rxc] -clock_fall -min -add_delay 1.200 [get_ports {RGMII_rd[*] RGMII_rx_ctl}]
set_input_delay -clock [get_clocks RGMII_rxc] -clock_fall -max -add_delay 1.200 [get_ports {RGMII_rd[*] RGMII_rx_ctl}]

#set_output_delay -clock [get_clocks rgmii_tx_clk] -max -1.0 [get_ports {rgmii_txd[*] rgmii_tx_ctl}]
#set_output_delay -clock [get_clocks rgmii_tx_clk] -min -0.8 [get_ports {rgmii_txd[*] rgmii_tx_ctl}] -add_delay
#set_output_delay -clock [get_clocks rgmii_tx_clk] -clock_fall -max -1.0 [get_ports {rgmii_txd[*] rgmii_tx_ctl}]
#set_output_delay -clock [get_clocks rgmii_tx_clk] -clock_fall -min -0.8 [get_ports {rgmii_txd[*] rgmii_tx_ctl}]

# False path constraints to async inputs coming directly to synchronizer
set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_reset_gen/*reset_sync*/PRE }]

#-----------------------------------------------------------
# To Adjust GMII Rx Input Setup/Hold Timing -
# These IDELAY Tap values are given for illustration -
# prupease modify as per design requirements -
#-----------------------------------------------------------
set_property IDELAY_VALUE 0 [get_cells -hier -filter {name =~ *design_1_gmii_to_rgmii_0_0_core/*delay_rgmii_rx_ctl}]
set_property IDELAY_VALUE 0 [get_cells -hier -filter {name =~ *design_1_gmii_to_rgmii_0_0_core/*delay_rgmii_rxd*}]
set_property IODELAY_GROUP gpr1 [get_cells -hier -filter {name =~ *design_1_gmii_to_rgmii_0_0_core/*delay_rgmii_rx_ctl}]
set_property IODELAY_GROUP gpr1 [get_cells -hier -filter {name =~ *design_1_gmii_to_rgmii_0_0_core/*delay_rgmii_rxd*}]
set_property IODELAY_GROUP gpr1 [get_cells -hier -filter {name =~ *i_design_1_gmii_to_rgmii_0_0_idelayctrl}]

 

Q : can someone please explain exactly what this timing failure means?

* I can see (in the excel sheet) a source clock rgmii_rx_clk involved, and a destination IDDR clocked by clk -> is this asynchronous clock domain crossing? (inter-clock path)

* I can also see something about multicycle path -> is this because of the IDELAY2 inserted on the path?

* also the routes are all '0' -> I did run implentation, I thought this includes place & route?

Q : so what else am I missing, and should I do to get rid of the timing issues? 

Q : also how do I determine the IDELAY_VALUE correctly? I've set it to zero.

 

btw, setup & hold times for the rx signals is 1.2ns according to the datasheet (delayed mode of operation)

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