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Explorer
Explorer
1,046 Views
Registered: ‎10-07-2016

Generation of IP-Core failed

Dear Xilinx users,

I'm using Vivado 2017.2 under Windows 7 64 bit, and I'm for some reasons no longer able to generate the output products for a self written IP-core named VTPG_0. When I generate the output products for my block design, I get the following error message:

 

Pic1.PNG

 

The strange thing is, when I reset the output products and clear the IP cache, the output products can be generated wihtout any issues. But after the output products were successfully generated, I'm not able to regenerate the output products. If I do so, I get the error message above.

 

Does anyone have an idea why this happens?

 

Best regards

Steffen

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3 Replies
Explorer
Explorer
982 Views
Registered: ‎10-07-2016

Re: Generation of IP-Core failed

As in the previous post, I thought that it was a path length issue, but it isn't. By accident it worked for on implementation run. But now after changing the implemenation strategy, I run into the same error messages again:

 

Pic2.png

 

That's really annoying...

 

Regards

Steffen

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Explorer
Explorer
800 Views
Registered: ‎10-07-2016

Re: Generation of IP-Core failed

Dear Xilinx users,

Is there nobody who can help on this problem?

I still try to find the root cause...

 

Regards

Steffen

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Adventurer
Adventurer
459 Views
Registered: ‎08-10-2017

Re: Generation of IP-Core failed

Hi Steffen,

Even I'm getting a similar error.

Were you able to figure out the solution ?

 

 

 

Regards

Jagannath

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