08-20-2013 12:05 PM
I am trying to develop a easily reconfigurable design by using multiple compiler directives at every point (Simulation, Synthesis) but now I am encountering a problem in Implementation.
The idea is as follows:
1. A global DEFINES.v file (attached) defines various global directives.
2. A second file called FPGA_UCFDefines.v (attached) looks at the DEFINES.V to see the definitions and accordingly directs the ISE tool to select appropriate .UCF file to go with design. The first line of the FPGA_UCFDefines.V calls to include the DEFINES.V file too.
Now the tool identifies the correct file and parses it but returns the following error in the .UCF file (attached), which to me is confusing because the same eact files works seamlessly if I were to add it to the design directly.
The error is as follows:
INFO:HDLCompiler:1693 - Analyzing Verilog file \"D:/MS1/Hardware/PrgLogic/Motherboard/OSPREY_7009/FPGA/RTL/Global/FPGA_UCFDefines.v\" into library work
INFO:ProjectMgmt - Include file found: 'D:/MS1/Hardware/PrgLogic/MotherBoard/OSPREY_7009/FPGA/RTL/Global/DEFINES.v' in file "D:/MS1/Hardware/PrgLogic/Motherboard/OSPREY_7009/FPGA/RTL/Global/FPGA_UCFDefines.v" line 1
INFO:ProjectMgmt - Include file found: 'D:/MS1/Hardware/PrgLogic/Motherboard/OSPREY_7009/FPGA/SYNTH_XILINX_FPGA_TOP/FPGA_V6LX240/MS1_OSPREY_SE_DUT64_LX240.ucf' in file "D:/MS1/Hardware/PrgLogic/Motherboard/OSPREY_7009/FPGA/RTL/Global/FPGA_UCFDefines.v" line 5
ERROR:HDLCompiler:806 - "D:/MS1/Hardware/PrgLogic/Motherboard/OSPREY_7009/FPGA/SYNTH_XILINX_FPGA_TOP/FPGA_V6LX240/MS1_OSPREY_SE_DUT64_LX240.ucf" Line 1: Syntax error near "#".
ERROR:ProjectMgmt:497 - 1 error(s) found while parsing design hierarchy.
In the files attached:
1. The DEFINES.V has two directives `DUT_SIZE_64 & `SE.
2. FPGA_UCFDefines.v looks at the two directives in the from the DEFINES.v and tries to include a .UCF file.
Any help in understanding the error is highly appreciated.
08-20-2013 02:08 PM
You can't do what you want this way. Anything you `include in Verilog will be interpreted as Verilog
source. The UCF files are not used at all during synthesis, and their syntax is nothing remotely
like Verilog, so you get this error. You can do something from the command line, using TCL for example.
08-20-2013 03:38 PM
Thanks a lot GSZAKACS for the reply.
I have never used TCL in any projects and this might be my opportunity to learn.
Can you give me some pointers or an example file as to how can I implement this thing?
08-21-2013 06:41 AM
I have to admit that I know nothing about TCL myself, but you can get a starting point from the
ISE Navigator GUI using Project --> Generate TCL script. This gives you a script that does
the build exactly as you would get running from the GUI. Then I'm afraid you're on your own
for figuring out how to edit this to do what you want. If it were me, I'd probably start by just
making several copies of this script and adjusting the ucf files in the "add_source_files"
procedure for each version you expect to build. If your options are too complex for this,
then you need to learn enough TCL to understand how to use switches to set the included
files. If you need to use the results of the Verilog pre-processor, then instead of the `includes
you'd need your Verilog source to do some file output to generate a file with the list of the
necessary UCF files that the TCL script can then import. Again I'm not up on TCL but I'm sure
you can find a way to do this.
08-21-2013 08:58 AM
Thanks a lot Gabor.
Lets see if how far can I go with the help of this info and adding various things to it.
If I figure it out I will come and post the script here.
08-22-2013 08:36 AM